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The system reset button has typically been connected indirectly to the PWROK input of the
PIIX4/PIIX4E. This technique will not reset the suspend well logic, which includes the
SMBus Host and Slave controllers. To reset the hardware in the suspend well, the reset button
should be connected to the RSMRST# input of the PIIX4/PIIX4E. Assertion of RSMRST#,
via a reset button, will result in a complete system reset. RSMRST# assertion will cause
SUS[A-C]# to assert which results in the deassertion of PWROK if SUS[A:C]# controls the
power supply PS-ON control signal. The deassertion of PWROK will cause the PIIX4/PIIX4E
to assert PCIRST#, RSTDRV, and CPURST.
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In the reference schematics, 3VSB is generated from 5VSB on the power supply connector.
The Zener diode, MMBZ5226BL, acts as a voltage regulator which clamps the standby
voltage at 3.3V. The 0.1uF and 10uF caps are for noise decoupling and the 56 ohm series
resistor is used for current limiting. This Zener diode and 56 ohm resistor should be validated
to make sure the standby voltage is clamped to 3.3V. The series resistor may need to be tuned
based on the standby current requirements of the board. As the 3VSB is required to supply
more current, the voltage will drop slightly. Also note that the Zener being used requires
approximately 20mA to sustain 3.3V, however a different Zener diode requiring less current
may be used. Refer to the schematics for implementation details.
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RI# can be connected to the modem if this feature is used. To implement ring indicate as a
wake event, the source driving the RI# signal must be powered when the PIIX4E suspend well
is powered.
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SUSC# is connected to PS-ON (pin 14) of the power supply connector through an inverter to
control the remote-off function.
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PCIREQ[3:0]# is connected between the PIIX4E and the PCI bus. Bus master request are
considered as power management events.
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Connect SMBCLK and SMBDATA to 2.7K ohm (approximate) pull-up resistors to VCC3, and
route to all DIMM sockets, PIIX4E, CKBF, LM79, LM75, and MAX1617. The 2.7K pull-up
may not be sufficient for all these loads and their associated trace lengths. This needs to be
considered on a design by design basis.
•
SMBALERT# is pulled up to 3VSB with an 8.2K ohm (approximate) resistor.
3.15.1
Power Button Implementation
The items below should be considered when implementing a power management model for a
desktop system. The power states are as follows:
S1 - POS (Power On Suspend - CPU context not lost)
S2 - POSCCL (Power On Suspend CPU Context Lost)
S3 - STR (Suspend To RAM)
S4 - STD (Suspend To Disk)
S5 - Soft-off
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Wake: Pressing the power button wakes the computer from S1-S5.
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Sleep: Pressing the power button signals software/firmware in the following manner:
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If SCI is enabled, the power button will generate an SCI to the OS.
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The OS will implement the power button policy to allow orderly shutdowns.
•
Do not override this with additional hardware.
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If SCI is not enabled:
•
Enable the power button to generate an SMI and go directly to soft-off or a supported sleep
state.
®
Intel
440GX AGPset Design Guide
Design Checklist
3-30
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