82093Aa (Ioapic) - Intel 440GX Design Manual

be stubbed off the trace run and must be as close as possible to the PIIX4/PIIX4E. The
capacitor must be no further than 0.5 inch from the PIIX4/PIIX4E. If a stub is required, it
should be kept to a few mm maximum length. The ground connection should be made
through a via to the ground plane, with no or minimal trace between the capacitor pad and
the via.
— Place the battery, 1K Ohm series current limit resistor, and the common-cathode isolation
diode very close to the PIIX4/PIIX4E. If this is not possible, place the common-cathode
diode and the 1K Ohm resistor as close to the 1uF capacitor as possible. Do not place
these components between the capacitor and the PIIX4. The battery can be placed
remotely from the PIIX4/PIIX4E.
— On boards that have chassis-intrusion utilizing external logic powered by the VCCRTC
pin, place the inverters as close to the common-cathode diode as possible. If this is not
possible, keep the trace run near the center of the board.
— Keep the PIIX4/PIIX4E VCCRTC trace away from the board edge. If this trace must run
from opposite ends of the board, keep the trace run towards the board center, away from
the board edge where contact could be made by people and equipment that handle the
board.
•
Recommendations for Existing Board Designs to minimize ESD events that may cause loss of
CMOS contents:
— The effectiveness of adding a 1uF capacitor, as identified above, needs to be determined
by examining the routing and placement. For example, placing the capacitor far from the
PIIX4 reduces its effectiveness.
3.17

82093AA (IOAPIC)

•
An I/O APIC is required for a DP system and is optional for a UP system.
•
The I/O APIC is a 5V device. All Vcc pins must be connected to 5V. Pins 19, 51 and 64 are 5V
power, and pins 1, 33 and 52 are ground pins.
•
APICCLK may be at 2.5V, 3.3V or 5V levels. If it is shared with the Slot 1 PICCLK then it
must be 2.5V. The maximum frequency is 16.666 MHz while the minimum is 14.3 MHz.
•
APICACK2# (pin 8) - This pin is connected to the Intel
•
CLK is compatible with 2.5V, 3.3V or 5V input levels. It is typically connected to the APIC
clocks that are 2.5V. The maximum frequency is 33 MHz while the minimum is 25 MHz.
•
SMI support - The option to route SMI through the IOAPIC in a Dual-Processor system is not
recommended due to timing constraints between the PIIX4E and the Slot 1 processors.
•
RTC Alarm Interrupt - When an IOAPIC is enabled, the IRQ8# output signal on the PIIX4E
reflects the state of IRQ8. IRQ8# resides in the PIIX4E suspend well and connects to INTIN8
on the IOAPIC. If the system is put in a STD or SOFF state, the PIIX4E will continue to drive
IRQ8 to the IOAPIC which could damage the IOAPIC if it is not powered. For this reason a
74LVC125 buffer is included in the schematics to isolate the IOAPIC's INTIN8 signal from the
PIIX4E's IRQ8# signal when the system is suspended.
•
System Timer Interrupt - When an IOAPIC is enabled, the PIIX4E IRQ0 output signal reflects
the state of the system timer interrupt. This signal should be connected to INTIN2 on the
IOAPIC, with no pull-up.
•
SCI and SMB Interrupts - The IRQ9OUT# output signal on the PIIX4E reflects the state of the
internally generated IRQ9 interrupt. The SCI and SMB interrupts are hardwired to IRQ9 in the
®
Intel 440GX AGPset Design Guide
Design Checklist
®
440GX AGPset WSC# signal.
3-32