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error, it does allow software diagnosis. Finally, the processor commences instruction
processing at the address in the vector. It is the responsibility of the error handler routine
to clean up the stack and determine where to continue execution.
If a bus error occurs during the exception processing for a bus error, an address error, or
a reset, the processor halts and all processing ceases. This halt simplifies the detection of
a catastrophic system failure, since the processor removes itself from the system to
protect memory contents from erroneous accesses. Only an external reset operation can
restart a halted processor.
Figure 4-7. Supervisor Stack Order for Bus or Address Error Exception
4.6.10 Address Error
An address error exception occurs when the processor attempts to access a word or long-
word operand or an instruction at an odd address. An address error is similar to an
internally generated bus error. The bus cycle is aborted, and the processor ceases current
processing and begins exception processing. The exception processing sequence is the
same as that for a bus error, including the information to be stacked, except that the
vector number refers to the address error vector. Likewise, if an address error occurs
during the exception processing for a bus error, address error, or reset, the processor is
halted.
4.6.11 Multiple Exceptions
When multiple exceptions occur simultaneously, they are processed according to a fixed
priority. Table 4-6 lists the exceptions, grouped by characteristics, with group 0 as the
highest priority. Within group 0, reset has highest priority, followed by address error and
then bus error. Within group 1, trace has priority over external interrupts, which in turn
takes priority over illegal instruction and privilege violation. Since only one instruction can
be executed at a time, no priority relationship applies within group 2.
MOTOROLA
15
LOWER
ADDRESS
ACCESS ADDRESS
PROGRAM COUNTER
R/W (READ/WRITE): WRITE = 0, READ = 1. I/N
(INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1.
MC68306 USER'S MANUAL
5
4
3
2
0
I/N FUNCTION CODE
R/W
HIGH
LOW
INSTRUCTION REGISTER
STATUS REGISTER
HIGH
LOW
EC33
4- 21
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