Double Bus Fault; Reset Operation; Figure 3-26. Halt Operation Timing Diagram - Motorola MC68306 User Manual

S0 S2 S4 S6 S0 S2 S4 S6
CLK
FC2–FC0
A31–A1
AS
LDS/UDS
R/W
DTACK
D15–D0
HALT
READ HALT READ

Figure 3-26. Halt Operation Timing Diagram

The single-step mode is derived from correctly timed transitions of HALT. HALT is negated
to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the
cycle completes. The single-step mode proceeds through a program one bus cycle at a
time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.

3.4.4 Double Bus Fault

When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
A retry operation does not initiate exception processing; a bus error during a retry
operation does not cause a double bus fault. The processor can continue to retry a bus
cycle indefinitely if external hardware requests.
A double bus fault occurs during a reset operation when a bus error occurs while the
processor is reading the vector table (before the first instruction is executed). The reset
operation is described in the following paragraph.

3.5 RESET OPERATION

RESET is asserted externally for the initial processor reset. Subsequently, the signal can
be asserted either externally or internally (executing a RESET instruction).
MOTOROLA MC68306 USER'S MANUAL 3- 27