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MPC Error Address Register
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
MERAD
MPC Error Attribute Register - MERAT
If the PERR or SERR bits are set in the MERST register, the contents of
the MERAT register are zero. If the MATO bit is set the register is defined
by the following figure:
Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
R
Reset
$00
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$FEFF0028
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
MERAD
R
$00000000
MPC Error Address. This register captures the MPC
address when the MATO bit is set in the MERST register.
It captures the PCI address when the SMA or RTA bits are
set in the MERST register. Its contents are not defined
when the PERR or SERR bits are set in the MERST
register.
$FEFF002C
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
R
$00
1
1
2
2
2
2
2
2
2
8
9
0
1
2
3
4
5
6
1
1
2
2
2
2
2
2
2
8
9
0
1
2
3
4
5
6
MERAT
Registers
2
2
2
2
3
3
7
8
9
0
1
2
2
2
3
3
7
8
9
0
1
2-41
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