Figure 6-5. Transmitter Timing Diagram - Motorola MC68306 User Manual

6.3.2.1 TRANSMITTER. The transmitters are enabled through their respective command
registers (DUCR) located within the serial module. The serial module signals the CPU
when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the
channel's status register (DUSR). Functional timing information for the transmitter is
shown in Figure 6-5.
The transmitter converts parallel data from the CPU to a serial bit stream on TxDx. It
automatically sends a start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The least significant bit is
sent first. Data is shifted from the transmitter output on the falling edge of the clock
source.
TxDx
TRANSMITTER
ENABLED
TxRDY
(SR2)
CS
1
CTS
(IP0)
2
RTS
(OP0)
NOTES:
1. TIMING SHOWN FOR MR2(4) = 1
2. TIMING SHOWN FOR MR2(5) = 1
3. C = TRANSMIT CHARACTER
N
4. W = WRITE
Following transmission of the stop bits, if a new character is not available in the transmitter
holding register, the TxDx output remains high ('mark' condition), and the transmitter
empty bit (TxEMP) in the DUSR is set. Transmission resumes and the TxEMP bit is
cleared when the CPU loads a new character into the transmitter buffer (DUTB). If a
disable command is sent to the transmitter, it continues operating until the character in the
MOTOROLA
C1 IN
TRANSMISSION
C1
W
W
C1 C2
MANUALLY ASSERTED
BY BIT- SET COMMAND

Figure 6-5. Transmitter Timing Diagram

MC68306 USER'S MANUAL
C2 C3
BREAK
W
W W
C3 START C4
BREAK
C4
W W
W
C5
STOP C6
NOT
BREAK
TRANSMITTED
MANUALLY
ASSERTED
C6
6-9