Fujitsu SPARC Enterprise T5440 Service Manual page 69

In the following example, POST reports a memory error at FB-DIMM location
/SYS/MB/CPU0/CMP0/BR1/CH0/D0. The error was detected by POST running on
core 7, strand 2.
show Command Output
EXAMPLE:
7:2>
7:2>ERROR: TEST = Data Bitwalk
7:2>H/W under test = /SYS/MB/CPU0/CMP0/BR1/CH0/D0
7:2>Repair Instructions: Replace items in order listed by 'H/W
under test' above.
7:2>MSG = Pin 149 failed on /SYS/MB/CPU0/CMP0/BR1/CH0/D0 (J792)
7:2>END_ERROR
7:2>Decode of Dram Error Log Reg Channel 2 bits
60000000.0000108c
7:2> 1 MEC 62 R/W1C Multiple corrected
errors, one or more CE not logged
7:2> 1 DAC 61 R/W1C Set to 1 if the error
was a DRAM access CE
7:2> 108c SYND 15:0 RW ECC syndrome.
7:2>
7:2> Dram Error AFAR channel 2 = 00000000.00000000
7:2> L2 AFAR channel 2 = 00000000.00000000
Perform further investigation if needed.
If POST detects a faulty device, the fault is displayed and the fault information is
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passed to the service processor for fault handling. Faulty FRUs are identified in
fault messages using the FRU name.
The fault is captured by the service processor, where the fault is logged, the
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Service Required LED is lit, and the faulty component is disabled. See
Fault Detected by POST on page
Run the ILOM show faulty command to obtain additional fault information.
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In this example, /SYS/MB/CPU0/CMP0/BR1/CH0/D0 is disabled. The system can
boot using memory that was not disabled until the faulty component is replaced.
Note – You can use ASR commands to display and control disabled components. See
"Disabling Faulty Components" on page
Related Information
"Diagnostic Flowchart" on page 13
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"POST Fault Management Overview" on page 22
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54.
55.
EXAMPLE:
Managing Faults 47