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Parallel Interface
Pin
Return
number
pin
number
1
19
2
20
3
21
4
22
5
23
6
24
7
25
8
26
9
27
10
28
C-2
Table C–1 Parallel interface signals
Signal
Direction
Compatible mode
Nibble mode
Data Strobe
Input
(DSTB)
Host Clock
Data 1
Input
Data 2
Input
Data 3
Input
Data 4
Input
Data 5
Input
Data 6
Input
Data 7
Input
Data 8
Input
Acknowledge
Output
(ACK)
Printer Clock
Description
• Strobe pulse for reading data (Data 1
to Data 8). The printer reads data
when this signals is low.
• The pulse width must be 1 µs or more
at the printer's receiving terminal.
This signal is set high when the host
requests the reverse data transfer phase
(nibble mode).
• Data 1 to 8 signals correspond to
parallel data bits 1 to 8.
• Data 8 is the most significant bit, but
is not used in the 7-bit ASCII mode.
• All signals must go high at least 1 µs
before the falling edge of the Data
Strobe signal, and must stay high for at
least 1 µs after the rising edge.
• Pulse signal indicating data receiption
completed (or data reception enabled)
status
• Issued when the printer switches from
offline to online
Reverse data transfer phase:
This signal goes high when data being
sent to the host is established.
Reverse idle phase:
This signal is set low then goes high to
interrupt the host, indicating that data is
available.
User's Manual
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