Fsb Frequency Select Signals (Bsel[2:0]); Fsb Signal Groups; Bsel[2:0] Encoding For Bclk Frequency; Fsb Pin Groups - Intel 500 - DATASHEET REV 003 Datasheet

For testing purposes, route the TEST3 and TEST5 signals through a ground referenced
Z = 55-Ω trace that ends in a via that is near a GND via and is accessible through an
0
oscilloscope connection.
3.6

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the chipset
system on the platform. The BSEL encoding for BCLK[1:0] is shown in
Table 3.

BSEL[2:0] Encoding for BCLK Frequency

BSEL[2]
L
L
3.7

FSB Signal Groups

In the following chapter, the FSB signals have been combined into groups by buffer
type. AGTL+ input signals have differential input buffers, which use GTLREF as a
reference level. The term AGTL+ Input refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, AGTL+ Output refers to the AGTL+ output
group as well as the AGTL+ I/O group when driving.
Two sets of timing parameters are specified because of a source synchronous data bus.
One set is for common clock signals that are dependent upon the rising edge of BCLK0
(ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
that are relative to their respective strobe lines (data and address) as well as the rising
edge of BCLK0.
Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle.
source synchronous, and asynchronous.
Table 4. FSB Pin Groups (Sheet 1 of 2)
Signal Group
AGTL+ Common Clock
Input
AGTL+ Common Clock I/O
AGTL+ Source
Synchronous I/O
22
BSEL[1] BSEL[0] BCLK Frequency
L L RESERVED
L H 133 MHz
Table 4
Type
Synchronous
to BCLK[1:0]
Synchronous
to BCLK[1:0]
Synchronous
to Associated
Strobe
identifies which signals are common clock,
Signals
5
BPRI#, DEFER#, PREQ#
DPWR#, TRDY#
ADS#, BNR#, BPM[3:0]#
DRDY#, HIT#, HITM#, LOCK#, PRDY#
Signals
REQ[4:0]#,
ADSTB[0]#
A[16:3]#
6
A[35:17]# ADSTB[1]#
D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
D[47:32]#, DINV2# DSTBP2#, DSTBN2#
D[63:48]#, DINV3# DSTBP3#, DSTBN3#
Electrical Specifications
Table 3.
1
, RESET#, RS[2:0]#,
3
, BR0#, DBSY#,
3
Associated Strobe
Datasheet