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Signal Definitions
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number
Ball
I/O
No.
Signal Name
(PU/PD)
A1
V
GND
SS
A2
V
PWR
IO
A3
AD30
I/O
D6
I/O
A4
PCICLK0
O
FPCI_MON
I
(PD
100
A5
REQ1#
I
(PU
22.5
A6
PCIRST#
O
A7
PCICLK
I
A8
IOW#
O
DOCW#
O
GPIO15
I/O
(PU
22.5
A9
GPIO20
I/O
(PU
22.5
DOCCS#
O
(PU
22.5
TFTD0
O
(PU
22.5
A10
GPIO17
I/O
(PU
22.5
IOCS0#
O
(PU
22.5
TFTDCK
O
(PU
22.5
A11
HSYNC
O
A12
AV
PWR
CCCRT
A13
V
GND
SS
A14
GREEN
O
A15
BLUE
O
A16
V
GND
SS
A17
V
PWR
PLL2
AMD Geode™ SC1200/SC1201 Processor Data Book
1
Buffer
Power
Type
Rail
Configuration
---
---
---
---
---
---
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
IN
,
PCI
O
PCI
O
V
---
PCI
IO
IN
Strap (See Table 3-
STRP
)
4 on page 44.)
IN
V
---
PCI
IO
)
O
V
---
PCI
IO
IN
V
---
T
IO
O
V
PMR[21] = 0 and
3/5
IO
PMR[2] = 0
O
PMR[21] = 0 and
3/5
PMR[2] = 1
IN
,
PMR[21] = 1 and
TS
)
PMR[2] = 1
O
3/5
IN
, O
V
3
(PMR[23]
= 0 and
T
3/5
IO
)
PMR[7] = 0) or
3
(PMR[23]
= 1 and
PMR[15] = 1 and
PMR[7] = 0)
O
3
(PMR[23]
= 0 and
3/5
)
PMR[7] = 1) or
3
(PMR[23]
= 1 and
PMR[15] = 1 and
PMR[7] = 1)
O
3
PMR[23]
= 1 and
1/4
)
PMR[15] = 0
IN
,
V
3
(PMR[23]
= 0 and
TS
IO
)
O
PMR[5] = 0) or
3/5
3
(PMR[23]
= 1 and
PMR[15] = 1 and
PMR[5] = 0)
O
3
(PMR[23]
= 0 and
3/5
)
PMR[5] = 1) or
3
(PMR[23]
= 1 and
PMR[15] = 1 and
PMR[5] = 1)
O
3
PMR[23]
= 1 and
1/4
)
PMR[15] = 0
O
V
---
1/4
IO
---
---
---
---
---
---
WIRE
AV
---
C-
CCRT
WIRE
AV
---
C-
CCRT
---
---
---
---
---
---
Ball
I/O
No.
Signal Name
(PU/PD)
6, 2
PD7
I/O
A18
TFTD13
O
F_AD7
O
A19
V
GND
SS
6, 2
PD6
I/O
A20
TFTD1
O
VOPD0
O
F_AD6
O
6, 2
PD1
I/O
A21
TFTD7
O
VOPD6
O
F_AD1
O
6, 2
STB#/WRITE#
O
A22
TFTD17
O
F_FRAME#
O
A23
CVBS
O
Y
O
TVG
O
A24
SVY
O
TVR
O
Cb
O
CVBS
O
A25
TVRSET
I
6
DPOS_PORT3
I/O
A26
6
DNEG_PORT3
I/O
A27
32579B
1
Buffer
Power
Type
Rail
Configuration
IN
,
V
3
PMR[23]
= 0 and
T
IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O
3
PMR[23]
= 1 and
1/4
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
---
---
---
IN
,
V
3
PMR[23]
= 0 and
T
IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O
3
(PMR[23]
= 1 and
1/4
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0
O
3
(PMR[23]
= 1 and
1/4
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
IN
,
V
3
PMR[23]
= 0 and
T
IO
O
(PMR[27] = 0 and
14/14
FPCI_MON = 0)
O
3
(PMR[23]
= 1 and
1/4
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
(PMR[23]
= 1 and
1/4
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
O
V
3
PMR[23]
= 0 and
14/14
IO
(PMR[27] = 0 and
FPCI_MON = 0)
1/4
3
O
PMR[23]
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
3
PMR[23]
= 0 and
14/14
(PMR[27] = 1 or
FPCI_MON = 1)
WIRE
AV
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
WIRE
AV
See F4BAR0+
CCTV
Memory Offset
C08h[4:3] bit
description on
page 356.
WIRE
AV
---
CCTV
IN
,
AV
---
USB
C-
O
CUSB
USB
IN
,
AV
---
USB
C-
O
CUSB
USB
29
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