Table 5-53. Bank 6 Register Map; Table 5-54. Bank 7 Register Map; Table 5-55. Bank 0 Bit Map - AMD Geode SC1200 Data Book

32579B
Offset Type
00h R/W
01h R/W
02h R/W
03h R/W
04h R/W
05h-07h ---
Offset Type
00h R/W
01h R/W
02h R/W
03h R/W
04h R/W
05h-06h ---
07h R/W
Register
Offset Name
00h RXD
TXD
01h 1
IER
TMR_IE
2
IER
02h 1
EIR
2 TMR_EV
EIR
FCR
03h LCR BKSE
BSR BKSE
04h
1
MCR
2
MCR
05h LSR ER_INF/
FR_END
06h MSR DCD
07h 1
SPR
2 CTE/PLD
ASCR
1. Non-extended mode.
2. Extended mode.
138

Table 5-53. Bank 6 Register Map

Name
IRCR3. IR Control 3
MIR_PW. MIR Pulse Width
SIR_PW. SIR Pulse Width
BSR. Bank Select
BFPL. Beginning Flags/Preamble Length
RSVD. Reserved

Table 5-54. Bank 7 Register Map

Name
IRRXDC. IR Receiver Demodulator Control
IRTXMC. IR Transmitter Modulator Control
RCCFG. Consumer IR (CEIR) Configuration
BSR. Bank Select
IRCFG1. IR Interface Configuration 1
RSVD. Reserved
IRCFG4. IR Interface Configuration 4

Table 5-55. Bank 0 Bit Map

7 6 5
RSVD
SFIF_IE TXEMP_
IE/PLD_IE
FEN[1:0]
SFIF_EV TXEMP_EV/
PLD_EV
RXFTH[1:0] TXFTH[1:0]
SBRK STKP
RSVD
MDSL[2:0]
TXEMP TXRDY
RI DSR
TXUR RXACT/
RXBSY
Bits
4 3
RXD[7:0] (Receive Data)
TXD[7:0] (Transmit Data)
MS_IE
DMA_IE MS_IE
RSVD RXFT
DMA_EV MS_EV
RSVD
EPS PEN
BSR[6:0] (Bank Select)
LOOP ISEN/
DCDLP
IR_PLS TX_DFR
BRK/ FE/
MAX_LEN PHY_ERR
CTS DDCD
Scratch Data
RXWDG/ TXHFE
LOST_FR
AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
2 1
LS_IE TXLDL_IE RXHDL_IE
LS_IE TXLDL_IE RXHDL_IE
IPR[1:0]
LS_EV/ TXLDL_EV RXHDL_EV
TXHLT_EV
TXSR RXSR FIFO_EN
STB WLS[1:0]
RILP RTS
DMA_EN RTS
PE/ OE
BAD_CRC
TERI DDSR
S_EOT FEND_INF RXF_TOUT
0
IPF
DTR
DTR
RXDA
DCTS