Table 6-3. Cycle Multiplexed Pci / Sub-Isa Balls - AMD Geode SC1200 Data Book

Core Logic Module
6.2.5.6 ROM Interface
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
8- or 16-bit wide ROM is supported. BOOT16 strap deter-
mines the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 4-2 on page 72 for
bit details) allows program control of the width.
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
6.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing
The SC1200/SC1201 processor multiplexes most PCI and
Sub-ISA signals on the balls listed in Table 6-3, in order to
reduce the number of balls on the device. Cycle multiplex-
ing is on a bus-cycle by bus-cycle basis (see Figure 6-6 on
page 152), where the internal Core Logic PCI bridge arbi-
trates between PCI cycles and Sub-ISA cycles. Other PCI
and Sub-ISA signals remain non-shared, however, some
Sub-ISA signals may be muxed with GPIO.
Sub-ISA cycles are only generated as a result of GX1 mod-
ule accesses to the following addresses or conditions:
• ROMCS# address range.
• DOCCS# address range.
• IOCS0# address range.
• IOCS1# address range.
• An I/O write to address 80h or to 84h.
• Internal ISA is programmed to be the subtractive decode
agent and no other agents claim the cycle.
If the Sub-ISA and PCI bus have more than four compo-
nents, the Sub-ISA components can be buffered using
74HCT245 or 74FCT245 type transceivers. The RD# (an
AND of IOR#, MEMR#) signal can be used as DIR control
while TRDE# is used as enable control.
AMD Geode™ SC1200/SC1201 Processor Data Book

Table 6-3. Cycle Multiplexed PCI / Sub-ISA Balls

(64 KB) and
32579B
PCI Sub-ISA
AD0 A0
AD1 A1
AD2 A2
AD3 A3
AD4 A4
AD5 A5
AD6 A6
AD7 A7
AD8 A8
AD9 A9
AD10 A10
AD11 A11
AD12 A12
AD13 A13
AD14 A14
AD15 A15
AD16 A16
AD17 A17
AD18 A18
AD19 A19
AD20 A20
AD21 A21
AD22 A22
AD23 A23
AD24 D0
AD25 D1
AD26 D2
AD27 D3
AD28 D4
AD29 D5
AD30 D6
AD31 D7
C/BE0# D8
C/BE1# D9
C/BE2# D10
C/BE3# D11
PAR D12
TRDY# D13
IRDY# D14
STOP# D15
DEVSEL# BHE#
Ball No.
U1
P3
U3
N1
P1
N3
N2
M2
M4
L2
L3
K1
L4
J1
K4
J3
E1
F4
E3
E2
D3
D1
D2
B6
C2
C4
C1
D4
B4
B3
A3
D5
L1
J2
F3
H4
J4
F1
F2
G1
E4
151