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Package Mechanical Specifications and Pin Information
4.3
Alphabetical Signals Reference
Table 15.
Signal Description (Sheet 1 of 8)
Name
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
BNR#
Datasheet
Type
A[35:3]# (Address) define a 2
space. In sub-phase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the Intel® Celeron® FSB.
Input/
A[35:3]# are source synchronous signals and are latched into the
Output
receiving buffers by ADSTB[1:0]#. Address signals are used as
straps which are sampled before RESET# is deasserted.
NOTE: When paired with a chipset limited to 32-bit
addressing, A[35:32] should remain unconnected
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-Mbyte boundary. Assertion of A20M# is only
Input
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# pins. All bus
Input/
agents observe the ADS# activation to begin parity checking,
Output
protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
Input/
Output
Signals
REQ[4:0]#, A[16:3]#
A[35:17]#
The differential pair BCLK (Bus Clock) determines the FSB frequency.
All FSB agents must receive these signals to drive their outputs and
latch their inputs.
Input
All external timing parameters are specified with respect to the rising
edge of BCLK0 crossing V
BNR# (Block Next Request) is used to assert a bus stall by any bus
Input/
agent who is unable to accept new bus transactions. During a bus
Output
stall, the current bus owner cannot issue any new transactions.
Description
36
-byte physical memory address
Associated Strobe
ADSTB[0]#
ADSTB[1]#
.
CROSS
53
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