Intel 500 - DATASHEET REV 003 Datasheet page 55

Package Mechanical Specifications and Pin Information
Table 15. Signal Description (Sheet 3 of 8)
Name
DBR#
DBSY#
DEFER#
DINV[3:0]#
DPRSTP#
DPSLP#
DPWR#
DRDY#
Datasheet
Type
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
Output debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for
Input/ driving data on the FSB to indicate that the data bus is in use. The
Output data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
Input
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of both FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals
are activated when the data on the data bus is inverted. The bus
agent inverts the data bus signals if more than half the bits, within
the covered group, would change level in the next cycle.
DINV[3:0]# Assignment to Data Bus
Input/
Bus Signal
Output
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
DPRSTP# is not used by the processor. For termination requirements
Input
please refer to the platform design guide.
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep state to the Deep Sleep state. In order to
Input
return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
driven by the Intel® ICH8M I/O controller.
DPWR# is a control signal used by the chipset to reduce power on
Input the processor data bus input buffers. This is not utilized by this
processor.
DRDY# (Data Ready) is asserted by the data driver on each data
Input/ transfer, indicating valid data on the data bus. In a multi-common
Output clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Description
Data Bus Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
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