Intel 500 - DATASHEET REV 003 Datasheet page 58

Table 15. Signal Description (Sheet 6 of 8)
Name
PRDY#
PREQ#
PROCHOT#
PSI#
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSVD
58
Type
Probe Ready signal used by debug tools to determine processor
debug readiness.
Output
Please refer to the appropriate platform design guide for more
implementation details.
Probe Request signal used by debug tools to request debug operation
of the processor.
Input
Please refer to the appropriate platform design guide for more
implementation details.
As an output, PROCHOT# (Processor Hot) goes active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This indicates
Input/
that the processor Thermal Control Circuit (TCC) has been activated,
Output
if enabled. As an input, assertion of PROCHOT# by the system
activates the TCC, if enabled. The TCC remains active until the
system deasserts PROCHOT#.
Processor Power Status Indicator signal. This signal is asserted when
Output
the processor is in a lower state (Deep Sleep).
PWRGOOD (Power Good) is a processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies
are stable and within their specifications. "Clean" implies that the
signal remains low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until
they come within specification.
Input
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
For termination requirements please refer to the appropriate
platform design guide.
REQ[4:0]# (Request Command) must connect the appropriate pins
Input/ of both FSB agents. They are asserted by the current bus owner to
Output define the currently active transaction type. These signals are source
synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
two milliseconds after V
specifications. On observing active RESET#, both FSB agents
Input
deassert their outputs within two clocks. All processor straps must be
valid within the specified setup time before RESET# is deasserted.
Please refer to the appropriate platform design guide for termination
requirements and implementation details. There is a 55-Ω (nominal)
on die pull-up resistor on this signal.
RS[2:0]# (Response Status) are driven by the response agent (the
Input agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
These pins are RESERVED and must be left unconnected on the
Reserved
board. However, it is recommended that routing channels to these
/No
pins on the board be kept open for possible future use. Please refer
Connect
to the appropriate platform design guide for more details.
Package Mechanical Specifications and Pin Information
Description
and BCLK have reached their proper
CC
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