Intel 500 - DATASHEET REV 003 Datasheet page 54

Table 15. Signal Description (Sheet 2 of 8)
Name
BPM[2:1]#
BPM[3,0]#
BPRI#
BR0#
BSEL[2:0]
COMP[3:0]
D[63:0]#
54
Type
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
Output
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[3:0]# should connect the
appropriate pins of all Celeron FSB agents.This includes debug or
Input/
performance monitoring tools.
Output
Please refer to the platform design guide for more detailed
information.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
Input the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are completed, then releases
the bus by deasserting BPRI#.
BR0# is used by the processor to request the bus. The arbitration is
Input/
done between processor (Symmetric Agent) and (G)MCH-M (High
Output
Priority Agent).
BSEL[2:0] (Bus Select) are used to select the processor input clock
frequency. Table 3
and the frequency associated with each combination. The required
frequency is determined by the processor, chipset and clock
Output
synthesizer. All agents must operate at the same frequency. The
Intel® Celeron® processor 500 series for platforms based on the
Mobile Intel® 965 Express Chipset family operates at a 533-MHz
system bus frequency (133-MHz BCLK[1:0] frequency).
COMP[3:0] must be terminated on the system board using precision
Analog (1% tolerance) resistors. Refer to the appropriate platform design
guide for more details on implementation.
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and are driven four times in a
common clock period. D[63:0]# are latched off the falling edge of
both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
correspond to a pair of one DSTBP# and one DSTBN#. The following
table shows the grouping of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
Input/
Data Group
Output
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
Package Mechanical Specifications and Pin Information
Description
defines the possible combinations of the signals
DSTBN#/
DINV#
DSTBP#
0
1
2
3
0
1
2
3
Datasheet