Related Manuals for Intel Pentium III Processor 512K
Summary of Contents for Intel Pentium III Processor 512K
- Page 1 ® ® Low Voltage Intel Pentium Processor 512K Dual Processor Platform Design Guide March 2002 Order Number: 273674-001...
- Page 2 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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Page 3: Table Of Contents
Meeting Dual Processor Power Requirements ..............33 5.4.1 Supplying Voltage ....................33 5.4.2 Decoupling Technology and Transient Response ..........33 Recommendations ......................35 ® ® 5.5.1 Decoupling Guidelines for LV Intel Pentium III Processor 512K Designs ..35 5.5.2 PLL Filter Recommendations ................36 Design Guide... - Page 4 14 CLKREF Filter Implementation ....................27 15 Single-Ended Clock BSEL Circuit (133 MHz) ................28 ® ® 16 Ideal LV Intel Pentium III Processor 512K Power Supply Scheme ........31 17 Power Distribution for a DP System Motherboard ..............31 18 Detailed Power Distribution Model .....................
- Page 5 14 Routing Guidelines ........................23 15 Component Values for SE Clocking Topology................26 16 CLKREF Component Values ......................27 17 BSEL[1:0] Encoding........................28 18 LV Intel Pentium processor 512K Bulk Capacitance Recommendations .......35 19 THERMTRIP# Timing Requirements..................38 20 AGTL Signals..........................40 21 CMOS Signals ..........................41 22 TAP/ITP Signals .........................42...
- Page 6 ® ® LV Intel Pentium III Processor 512K Dual Processor Platform Revision History Date Revision Description March 2002 First release of this document. Design Guide...
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Page 7: Introduction
Design Considerations are suggestions for platform design. These provide one way to meet the design recommendations. They are based on the reference platforms designed by Intel. They could be used as an example, but may not be applicable to your particular design. -
Page 8: Conventions And Terminology
Keep-out zone - The area on or near a Micro FCBGA packaged processor that system designs can not utilize. • Processor - For this document, the term processor is the generic form of the LV Intel Pentium processor 512K for the Micro FCBGA package. Design Guide... -
Page 9: General Design Considerations
If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design. Any deviation from the guidelines should be simulated. Even when the guidelines are followed, Intel recommends that you simulate critical signals to ensure proper signal integrity and flight time. -
Page 10: Micro-Fcbga Component Keepout
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Additional guidelines on board stack-up, placement, and layout include the following. The board impedance (Z) should be between 49.5 Ω and 60.5 Ω (55 Ω ± 10% is •... -
Page 11: Micro-Fcbga Package Mechanical Specifications
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Table 2. Micro-FCBGA Package Mechanical Specifications Symbol Parameter Unit Overall height, as delivered (1) 2.27 2.77 Die height 0.854 Ball diameter 0.78 Package substrate length 34.9 35.1 Package substrate width 34.9... -
Page 12: Micro-Fcbga Package - Top And Bottom Isometric Views
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Figure 3. Micro-FCBGA Package – Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA This page intentionally left blank. LABEL TOP VIEW BOTTOM VIEW Design Guide... -
Page 13: Processor Host Bus Design
Table 5 provides recommended values for system timings. Skew and jitter values for the clock generator device come from the clock driver vendor’s datasheet. The PCB skew specification is based on the results of extensive simulations performed by Intel engineers. The T value is based on Intel’s experience with systems that use previous generations of processors. -
Page 14: General Topology And Layout Guidelines
<= 7.5 - 3.25 - 0.95 - 0.25 - 0.2 - 0.5 = 2.35 ns flight,max General Topology and Layout Guidelines Intel recommends that all LV Intel Pentium processor 512K dual-processing platforms use a system bus T-topology. Figure 4 shows a high level diagram of this topology. The pull-up resistors shown inside the processor packages are the processor’s on-die AGTL termination, since the LV... -
Page 15: Wired-Or Signal Considerations
Figure 5. This recommendation will work correctly for systems designed with the standard T topology. Please note that the incorporation of Wired-OR termination is optional. Intel has not seen any system failures on systems which do not implement the Wired-OR termination recommendations. -
Page 16: Simulation Methodology
Choosing a value at the lower end of the range (around 100 Ω), provides optimal dampening but has a larger impact on the signal flight times. Intel recommends a value of 150 Ω ±10% as a reasonable tradeoff between dampening and flight time. -
Page 17: Trace Routing
Pentium III Processor 512K Dual Processor Platform Intel recommends running simulations at the device pads for signal quality and at the device pins for timing analysis. However, simulation results at the device pins may be used later to correlate simulation performance against actual system measurements. -
Page 18: Layout Rules For Non-Agtl (Cmos) Signals
® ® LV Intel Pentium III Processor 512K Dual Processor Platform routing between component pins. Minimize the distance that traces have to be close and parallel to each other, and maximize the distance between the sections when the spacing restrictions relax. -
Page 19: Debug Port Routing Guidelines
LV Intel Pentium processor 512K performance, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot. -
Page 20: Simple Terminations
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Table 10. System Signal Layout Guidelines Signal Routing Notes Sample Layout Route with normal trace 2 to 6 inches to the debug port POWERON Figure 6a connector BCLK, BCLK#... -
Page 21: Tck Termination, Dp System
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Figure 7. TCK Termination, DP System Figure 3. TCK Termination, DP System Execution Signal Layout Guidelines Table 12. Execution Signals Routing Guidelines Signal Routing Notes Sample Layout PREQx# AGTL signal routing guidelines apply... -
Page 22: Reset# Signal Termination
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Figure 9. RESET# Signal Termination Debug Port Load Load RESET# Source 3.9.1.2 Signal Termination Requirements Table 13 lists signal termination requirements for the debug port signals. Table 13. Debug Port Termination Requirement... -
Page 23: Jtag Signals Tdi/Tdo For Processor Only
® ® LV Intel Pentium III Processor 512K Dual Processor Platform 3.9.1.3 Routing Guidelines Table 14. Routing Guidelines Parameter Reference Figure Description 1" max from debug port to RT AND 12" max from debug port to Figure 7 processor VERY SENSITIVE TO NOISE -- please route accordingly... -
Page 24: Clocking
If necessary, grounded guard band traces can be routed next to clock traces to reduce crosstalk to other signals. Figure 11 shows the host bus clocking connections that must be made in a LV Intel Pentium processor 512K system. Detailed information regarding the routing, layout, and termination of the processor and chipset connections can be found in “Single Ended Host Bus Clocking Routing”... -
Page 25: Single Ended Host Bus Clocking Routing
“CLKREF Filter Implementation” on page 27. Figure 12 shows the topology that should be used for the LV Intel Pentium processor 512K clock traces. Please note that L0, L1, and L2 refer to trace lengths between the illustrated components. -
Page 26: Component Values For Se Clocking Topology
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Table 15. Component Values for SE Clocking Topology Reference Value Notes 0.25” to 0.5” You may flood this area Match processor 0 and processor 1 L1 lengths as close as 5”... -
Page 27: Clkref Filter Implementation
4.2.1 CLKREF Filter Implementation When using single-ended clocking mode, the BCLK#/CLKREF signal on the LV Intel Pentium processor 512K serves as a reference voltage to the clock input. To provide a steady reference voltage, a filter circuit must be implemented and attached to this pin. Figure 14 shows the recommended CLKREF filter implementation. -
Page 28: Single-Ended Clocking Bsel[1:0] Implementation
III Processor 512K Dual Processor Platform 4.2.2 Single-Ended Clocking BSEL[1:0] Implementation In a LV Intel Pentium processor 512K platform that uses single-ended (SE) clocking or a clock source that does not support the VTT_PWRGD protocol, the normal BSEL frequency selection process does not work. -
Page 29: Debug Port Host Clock Connection
However, since proper decoupling and noise-free power delivery are critical to the clock driver’s operation, Intel encourages system implementors to carefully follow the chipset and clock driver vendor’s recommendations in these areas. An incorrect implementation of these circuits can easily cripple a clock driver’s ability to produce... -
Page 30: Power
The terms “AGTL” and “system bus” are synonymous. “VRM 8.5” refers to the voltage regulator for the LV Intel Pentium processor 512K. It is a DC-DC converter that supplies the required voltage and current to each processor. -
Page 31: Ideal Lv Intel ® Pentium ® Iii Processor 512K Power Supply Scheme
However, due to the load-line characteristics specified for the LV Intel Pentium Processor 512K, Intel recommends that separate power planes be utilized. This configuration of voltage regulators is shown in Figure 17. Figure 17. Power Distribution for a DP System Motherboard... -
Page 32: Intel ® Pentium ® Iii Processor 512K Power Requirements
CORE voltages from +1.05 V to +1.825 V. The VRM 8.5 voltage regulator can provide adequate power for all speed versions of the LV Intel Pentium processor 512K. Refer to the VRM 8.5 DC-DC Converter Design Guidelines document for available voltage details. -
Page 33: Voltage Sequencing
Processor 512K Datasheet. Meeting Dual Processor Power Requirements Intel recommends that designers use a VRM 8.5 compliant regulator for LV Intel Pentium processor 512K baseboard designs. Place high frequency and bulk decoupling capacitors as needed between the VRM 8.5 and the processor to ensure voltage fluctuations remain in specification. -
Page 34: 1206 Capacitor Pad And Via Layouts
Use thorough analysis when choosing these components. 5.4.2.1 Location of High-Frequency Decoupling A system designer for the LV Intel Pentium processor 512K should properly design for high-frequency decoupling. High-frequency decoupling should be placed as close to the power pins of the processor as physically possible. If necessary, use both sides of the board for placing components;... -
Page 35: Recommendations
3.1 nH max 5.04 A rms Recommendations Intel recommends using simulation to design and verify LV Intel Pentium processor 512K systems. With the estimates provided in the previous section, a model of the power source, and the model of the processor, system developers can begin analog modeling. The following sections contain Intel’s design recommendations. -
Page 36: Pll Filter Recommendations
5.5.2 PLL Filter Recommendations It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements. A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled power source for the internal PLL. -
Page 37: Pll Power Low Pass Filter Response
® ® LV Intel Pentium III Processor 512K Dual Processor Platform 5.5.2.2 Filter Specification The function of the filter is to protect the PLL from external noise through low-pass attenuation. The low-pass specification, with input at V and output measured across the capacitor, is as follows: •... -
Page 38: Thermals
1/2 Nominal V 5.0 seconds THERMTRIP# Erratum Intel has identified an issue with THERMTRIP# which may incorrectly assert during de-assertion of RESET# at nominal operating temperatures in LV Intel Pentium processor 512K A-1 stepping processors. The assertion of THERMTRIP# with cause the processor to shut down internally and stop execution. -
Page 39: Intel Pentium
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Figure 23. LV Intel Pentium processor 512K Example THERMTRIP# Workaround Circuit 2.5V 330 ohm PWRGD CPU0 CPU1 150 ohm 0 ohm 680 ohm CPU1 CPU2 39 ohm PWRGD NOTES: 1. -
Page 40: System Design Checklist
Introduction This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements a LV Intel Pentium processor 512K system design. This is not a complete list and does not guarantee that a design will function properly. -
Page 41: Cmos (Non-Agtl) Signals
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Table 20. AGTL Signals (Sheet 2 of 2) CPU Pin Pin Connection LOCK# (V3) Connect to chipset and second CPU. REQ[4:0]# Connect to chipset and second CPU. to match AGTL trace impedance which is typically 68 Ω, Terminate to V connect to chipset. -
Page 42: Tap/Itp Checklist
Host bus clocks are critical. Signal integrity and timing of these signals should be carefully evaluated and simulated. Intel strongly recommends that system bus clocks be routed on signal layers next to the ground layer and that they do not traverse multiple signal layers. - Page 43 The table below shows the encoding scheme for BSEL[1:0]. The only supported ® ® system bus frequency for the LV Intel Pentium Processor 512K (1.15 V) is 133 MHz. If another frequency is used, the processor is not guaranteed to function properly.
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Page 44: Power Signals
® ® LV Intel Pentium III Processor 512K Dual Processor Platform Table 25. Power Signals CPU Pin Pin Connection TESTHI[2:1] Connect individually to V through a 1 KΩ pull-up resistor. TESTLO[2:1] Connect to Ground through a 1 KΩ pull-down resistor.