Intel 500 - DATASHEET REV 003 Datasheet page 60

Table 15. Signal Description (Sheet 8 of 8)
Name
TRDY#
TRST#
V
CC
V
CCA
V
CCP
V
CC_SENSE
VID[6:0]
V
SS_SENSE
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Type
TRDY# (Target Ready) is asserted by the target to indicate that it is
Input ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
Input
must be driven low during power on Reset.
Input Processor core power supply.
Input V provides isolated power for the internal processor core PLL's.
CCA
Input Processor I/O Power Supply.
V together with V
CC_SENSE
Intel® MVP 6 that control the 2.1-mΩ loadline at the processor die.
Output
It should be used to sense or measure power near the silicon with
little noise.
VID[6:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (V
processors, these are CMOS signals that are driven by the processor.
The voltage supply for these pins must be valid before the VR can
Output supply V to the processor. Conversely, the VR output must be
CC
disabled until the voltage supply for the VID pins becomes valid. The
VID pins are needed to support the processor voltage specification
variations. See Table 2
supply the voltage that is requested by the pins, or disable itself.
V together with V
SS_SENSE
Intel MVP 6 that control the 2.1-mΩ loadline at the processor die. It
Output
should be used to sense or measure ground near the silicon with little
noise.
Package Mechanical Specifications and Pin Information
Description
are voltage feedback signals to
SS_SENSE
). Unlike some previous generations of
CC
for definitions of these pins. The VR must
are voltage feedback signals to
CC_SENSE
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Datasheet