Fujitsu ULTIMA90 Maintenance Manual page 148

The MB91110 has the chip select address decoder circuits for memory control as shown in Figure 5.3.7
[Chip select address decoder]
The chip select address decoder decodes addresses and outputs a chip enable signal to ROM.
The memory circuit consists of four types of elements, SRAM, PROGRAM ROM, and EEPROM as shown in
Figure 5.3.7.
[SRAM]
The MB91110 has a "256K x 16 bits" DRAM for control program work areas, line buffers, and external character storage areas.
[EEPROM]
The MB91110 has a 16K-bit serial transmission EEPROM (equivalent to the BR24LFV-W) that contains setup
information, mechanism information, and consumables information.
If the board is replaced, remove the EEPROM from the board to be replaced and mount it on the replacing board.
[ROM]
The MB91110 uses a "2M x 16 bits" flash ROM for programs.
It also permits another flash ROM to be mounted when needed to support various types of emulation.
A 4-megabyte memory space is defined for each ROM.
Address
00000000 to 000007FF
00100000 to 003FFFFF
00400000 to 007FFFFF
00800000 to 00BFFFFF
Figure 5.3.7 Memory control block diagram
Capacity
2K bytes
3M bytes
4M bytes
4M bytes
148
Explanation
CPU internal I/O area
External I/O area (for FPGA)
Program ROM 1
CG ROM area