Voltage Supply; Power Management States; Power Supply Rail Descriptions; Table 109. Power Management States On Intel Reference Board - Intel 855GM Design Manual

R
13.3.

Voltage Supply

13.3.1.

Power Management States

Table 109. Power Management States on Intel Reference Board

Signal
S0 (FULL ON)
S1M (POS)
S3 (STR)
S4 (STD)
S5 (Soft Off)
13.3.2.

Power Supply Rail Descriptions

Table 110. Power Supply Rail Descriptions on Intel Reference Board

Signal Names
+V1_25
+V1_5
+V1_5S
+V1_5ALWAYS
+V1_8S
+V1_2S for
855GM
+V1_35S for
855GME
+V2_5
®
Intel 855GM/855GME Chipset Platform Design Guide
Intel 855GM/GME Chipset Based System Power Delivery Guidelines
SLP_S SLP_S3# SLP_S4#
1#
HIGH HIGH HIGH
LOW HIGH HIGH
LOW LOW HIGH
LOW LOW LOW
LOW LOW LOW
Voltage Current
(V) (A)
1.25 0.01
1.5 0.03
1.5 1.35
1.5 0.1
1.8 0.6
1.2 1.8
1.35
2.5 8.12
SLP_S5# +V*ALW
HIGH ON
HIGH ON
HIGH ON
HIGH ON
LOW ON
Tolerance Enable
+/- 3.2% SLP_S3# - HIGH
SLP_S4# - HIGH
+/- 5% SLP_S4# - HIGH
+/- 5% SLP_S3# - HIGH
+/- 5% +V3ALWAYS
+/- 5% SLP_S3# - HIGH
+/- 5% SLP_S3# - HIGH
+/- 5% SLP_S4# - HIGH
+V* +V*S Clocks
ON ON ON
ON ON LOW
ON OFF OFF
OFF OFF OFF
OFF OFF OFF
Description
GMCH, DDR
Termination
DDR Reference (VREF)
LAN logic
CPU VCCA (Intel
Pentium M Processor
on 90 nm Process with
2 MB L2 Cache only)
GMCHDVO-Core,
GMCH DLVDS, GMCH
DAC, GMCH ALVDS,
ICH4-M core, ICH4-M
VCCHL
ICH4-M Resume
CPU VCCA (Intel
Pentium M Processor
only)
GMCH Core, GMCH
HL, GMCH DPLL,
GMCH HPLL, GMCH
GPLL, GMCH VCCASM
GMCH DDR I/O, DDR
SO-DIMM, GMCH
1
TXLVDS
257