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Intel Pentium M/Celeron M Front Side Bus Design Guidelines
4.3.1.3.
ITP700FLEX Design Guidelines for Production Systems
For production systems that do not populate the onboard ITP700FLEX debug port connector, the
following guidelines should be followed to ensure that all necessary signals are terminated properly.
Table 18 summarizes all the signals that require termination when a system does not populate the
ITP700FLEX connector but still implements the routing for all the signals. This includes TDI, TMS,
TRST#, and TCK. Based on the recommended values in this table, the resistor tolerances for TMS and
TCK can be relaxed from ±1% to ±5% to reduce cost. Also, TDO can be left as a no connect, thus the
54.9 Ω ±1% pull-up and 22.6 Ω ±1% series resistors can be removed.
For the ITP700FLEX connector's RESET# input signal, the 220 Ω ±5% resistor should be removed as
well as the 22.6 Ω ±1% series resistor.
The series 33 Ω and
host clock inputs to the ITP700FLEX connector can also be depopulated for production systems. The
only requirement is that the BIOS should disable the third differential host clock pair routed from the
CK-408 clock chip to the ITP700FLEX connector.
Finally, the 150 Ω to 240 Ω pull-up resistor for the DBR# output signal from the ITP700FLEX
connector may or may not be depopulated depending on how it affects the system reset logic that it is
connected to. Thus, it is the responsibility of the system designer to determine whether termination for
DBR# is required or not for a given system implementation. The same is also true for DBA#, if
implemented. This signal is not required and can be left as no connect. However, it is the responsibility
of the system designer to determine whether termination for DBA# is required or not.
4.3.2.
Recommended ITP Interposer Debug Port Implementation
Intel is working with American Arium* to provide ITP interposer cards for use in debugging processor
based systems as an alternative to the onboard ITP700FLEX in cases where the onboard connector
cannot be supported. The ITP interposer card is an additional component that integrates the processor
socket along with ITP700 connector on a single interposer card that is compatible with the 478-pin Intel
Pentium M / Intel Celeron M processor socket.
Table 18 summarizes all the signals that require termination for a system designed for use with the ITP
interposer. This includes TDI, TMS, TRST#, and TCK. TDO can be left as a no connect.
DBR# should be routed to the system reset logic (e.g. the SYSRST# signal of the ICH4-M) and initiate
the equivalent of a front panel reset commonly found in desktop systems. The 150 Ω to 240 Ω pull-up
resistor should be placed within
cycled when DBR# is asserted.
DBA# is an optional system signal that can be used to indicate to the system that the ITP/TAP port is
being used. If not implemented, this signal can be left as no connect. If implemented, it should be routed
with a 150 Ω to 240 Ω pull-up resistor placed within 1ns of the ITP connector., it should be routed with
a 150 Ω to 240 Ω pull-up resistor placed within 1ns of the ITP connector.
4.3.2.1.
ITP_CLK Routing to ITP Interposer
A layout example for ITP_CLK/ITP_CLK# routing to the CPU socket for supporting an ITP interposer
is shown in Figure 32. The CK-408 clock chip is mounted on the primary side layer of the motherboard
and the differential clock pair also breaks out on the same side. The differential ITP clock pair routing
72
Ω ±1% parallel termination resistors on the ITP_CLK/ITP_CLK# differential
49.5
5.5"
of the ITP connector. Note that the processor should not be power
Intel
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855GM/855GME Chipset Platform Design Guide
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