Edo Dram Array - Intel AC450NX Product Manual

AC450NX Rack Server System Product Guide

EDO DRAM Array

The extended data out (EDO) DRAM array on the memory module consists of sixteen 72-bit
(64-bit data plus 8 ECC bits) DIMM sockets. They are divided into four memory banks, A–D, of
four sockets each. These banks support only 4:1 interleaving (DIMMs in all four sockets). For
example, in bank A socket
•
J1 contains interleave 0
•
J2 contains interleave 1
•
J3 contains interleave 2
•
J4 contains interleave 3
Because each interleave provides access to 72 bits of data, 4:1 interleaving yields 288 bits
(32 bytes) per DRAM transaction—one cache line for the processor. If the CPU baseboard
contains two 4:1 interleaving memory modules, successive DRAM transactions occurring in the
different memory modules complete at a maximum rate of one transaction every 30 ns. This yields
a maximum data rate of 1.067 GB per second.
Although several DIMM population options are available, the following table lists the populations
that should be used to add memory to the system.
Table 19-1. Memory Module DIMM Support
Category
Speed
Capacity/Organization/Refresh
Voltage
Data Width
Page Mode
Buffered/Non
Maximum Height
DRAM Package
* The memory module supports only CAS-before-RAS refresh. When selecting a module, make sure that the target
refresh number corresponds to CBR refresh.
All DIMMs within a given bank must be identical. From bank to bank, the 450NX PCI chipset
supports different varieties of DIMM sizes, manufacturers, and speeds.
Only configuration adhering to the following rules are validated, and they are the only
configuration that are fully supported:
•
All DIMMs within a given back must be identical.
•
Install 32, 64, and 256 MB DIMMs in the memory banks.
•
The total number of DIMMs on both memory modules: 4, 8, 16, 24, or 32 (two memory
module configuration).
•
The total number of DIMMs using only one memory module must be: 4, 8, 12, or 16 (one
memory module and one memory terminator configuration).
234
Supported DIMM Variety
50 ns, 60 ns
32 MB: 16 Mbit, 4Mx4 DRAM; 2 K or 4 K refresh
64 MB: 64 Mbit, 8Mx8 DRAM; 4 K refresh
256 MB: Double-high; 64 Mbit, 16Mx4 DRAM; 4K or 8K refresh
3.3 V
x72 (ECC)
EDO
Buffered
2.4 inches
TSSOP
*
*
*