Characteristics - Omron SYSMAC CPM2B-S001M-DRT Operation Manual

Specifications
2-1-2
Control method
I/O control method
Programming language
Instruction length
Instructions
Execution time
Program capacity
Max. I/O capac-
ity
Input bits
Output bits
Work bits
Special bits (SR area)
Temporary bits (TR area)
Holding bits (HR area)
Auxiliary bits (AR area)
Link bits (LR area)
Timers/Counters
CompoBus/S Master functions
DeviceNet Slave functions
Data memory
Interrupt
processing
High-speed
counter
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Characteristics

Item
Stored program method
Cyclic scan with direct output (Immediate refreshing can be performed with
IORF(97).)
Ladder diagram
1 step per instruction, 1 to 5 words per instruction
Basic instructions 14
Special 105 instructions, 185 variations
instructions
0.64 µs (LD instruction)
Basic instructions
7.8 µs (MOV instruction)
Special
instructions
4,096 words
CPU Board only 74 points
With Expansion 170 points max.
I/O Boards
IR 00000 to IR 00915 (Words not used for input bits can be used for work bits.)
IR 01000 to IR 01915 (Words not used for output bits can be used for work bits.)
928 bits: IR 02000 to IR 04915 and IR 20000 to IR 22715
448 bits: SR 22800 to SR 25515
8 bits (TR0 to TR7)
320 bits: HR 0000 to HR 1915 (Words HR 00 to HR 19)
384 bits: AR 0000 to AR 2315 (Words AR 00 to AR 23)
256 bits: LR 0000 to LR 1515 (Words LR 00 to LR 15)
256 timers/counters (TIM/CNT 000 to TIM/CNT 255)
Up to 32 Slaves can be connected and up to 256 I/O points can be controlled.
DeviceNet Remote I/O Link
Use up to 1,024 I/O points in the I/O Link.
Explicit Message Communications
Any PC data area can be accessed from the Master.
Read/Write 2,048 words (DM 0000 to DM 2047) The Error Log is contained in DM 2000 to
DM 2021.
Read-only 456 words (DM 6144 to DM 6599)
PC Setup 56 words (DM 6600 to DM 6655)
External interrupts 2 (Also used for external interrupt inputs in counter mode and quick-response
inputs.)
Interval timer 1 (Scheduled Interrupt Mode or Single Interrupt Mode)
interrupts
High-speed counter 1 (20 kHz single-phase or 5 kHz two-phase (linear count method))
Counter interrupt 1 (set value comparison or set-value range comparison)
Interrupt Inputs 2 inputs (Also used for interrupt inputs and quick-response inputs.)
(Counter mode)
Counter interrupts 2 (Also used for the external interrupt inputs and quick-response inputs.)
CPU Boards
1-ms timers: TMHH(– –)
10-ms timers: TIMH(15)
100-ms timers: TIM
1-s/10-s timers: TIML(– –)
Decrementing counters: CNT
Reversible counters: CNTR(12)
Section 2-1
23