Characteristics - Omron SYSMAC CPM1 Operation Manual

Specifications

2-1-2 Characteristics

Item
Control method
I/O control method
Programming language
Instruction length
Types of instructions
Execution time
Program capacity
Input bits
Output bits
Work bits
Special bits (SR area)
Temporary bits (TR area)
Holding bits (HR area)
Auxiliary bits (AR area)
Link bits (LR area)
Timers/Counters
Data memory
Interrupt processing
Input interrupts
Interval timer interrupts
Memory protection
Memory backup
Self-diagnostic functions
Program checks
High-speed counter
Quick-response inputs
Input time constant
Analog volume settings
CPM1-10CDR-j
Stored program method
Cyclic scan with direct output; immediate refresh processing
Ladder diagram
1 step per instruction, 1 to 5 words per instruction
Basic instructions: 14
Special instructions: 77 types, 134 instructions
0.72 to 16.2 µs
Basic instructions:
Special instructions: 16.3 µs (MOV instruction)
2,048 words
00000 to 00915 (Words not used for input bits can be used for work bits.)
01000 to 01915 (Words not used for output bits can be used for work bits.)
512 bits: 20000 to 23115 (Words IR 200 to IR 231)
384 bits: 23200 to 25515 (Words IR 232 to IR 255)
8 bits (TR0 to TR7)
320 bits: HR 0000 to HR 1915 (Words HR 00 to HR 19)
256 bits: AR 0000 to AR 1515 (Words AR 00 to AR 15)
256 bits: LR 0000 to LR 1515 (Words LR 00 to LR 15)
128 timers/counters (TIM/CNT 000 to TIM/CNT 127)
100-ms timers: TIM 000 to TIM 127
10-ms timers (high-speed counter): TIM 000 to TIM 127 (see note)
(the timer numbers used are the same as for the 100-ms timers)
Decrementing counters and reversible counters
Read/Write: 1,024 words (DM 0000 to DM 1023)
Read-only: 512 words (DM 6144 to DM 6655)
External interrupts: 2
(Response time: 0.3 ms max.)
2
1 (0.5 to 319,968 ms in Scheduled Interrupt Mode or Single Interrupt Mode)
HR and read/write DM area contents; and counter values maintained during power
interruptions.
Flash memory:
The program, read-only DM area, and PC Setup area are backed up without a battery.
Capacitor backup:
The read/write DM area, error log area, HR area, and counter values are backed up by a
capacitor for 20 days at 25_C. The capacitor backup time depends on the ambient
temperature. See the graph on the following page for details.
CPU Unit failure (watchdog timer), I/O bus error, and memory failure
No END instruction, programming errors (continuously checked during operation)
One high-speed counter: 5 kHz single-phase or 2.5 kHz two-phase (linear count method)
Increment mode: 0 to 65,535 (16 bits)
Up/Down mode: –32,767 to 32,767 (16 bits)
The same inputs are used for quick-response inputs and external interrupt inputs.
(Min. input pulse width: 0.2 ms)
Can be set to 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, 32 ms, 64 ms, or 128 ms.
2 controls (0 to 200 BCD)
Note Use TIM 000 to TIM 003 when creating a timer using the high-speed timer
instruction to perform interrupt processing.
CPM1-20CDR-j
External interrupts: 4
(Response time: 0.3 ms max.)
4
Section 2-1
CPM1-30CDR-j(-V1)
17