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6.2.1
PCIe Design Guidelines
Table 6-9 and Figure 6-8 provide the signal routing requirements for the PCIe interface.
Table 6-9.
PCIe Interface Signal Routing Requirements
Parameter
Specification
Data rate / UI period
Configuration / device organization
Topology
Termination
Impedance
Trace Impedance (diff / SE)
Reference plane
Spacing
Trace Spacing (Stripline/Microstrip)
pair – pair
To plane and capacitor pad
To unrelated high-speed signals
Length/Skew
Trace loss characteristic @ 2.5 GHz
Breakout region (max length)
Max trace length/delay
Max PCB via distance from the BGA
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between subsequent
discontinuities
Differential pair uncoupled length
Via
Via placement
Max # of vias
PTH vias
Micro-vias
Max via stub length
Routing signals over antipads
AC Cap
Value (Min/Max)
Location (max length to adjacent discontinuity)
NVIDIA Jetson TX2 NX
Requirement
Units
5.0 / 200
Gbps / ps
1
Load
Point-point
50
Ω
85 / 50
Ω
GND
3x / 4x
Dielectric
3x / 4x
3x / 4x
< 0.7
dB/in
41.9
ps
5.5 (880)
in (ps)
41.9
ps
0.15 (0.5)
mm (ps)
0.15 (0.5)
mm (ps)
41.9
ps
Place GND vias as symmetrically as possible to data pair vias. GND via
distance should be placed less than 1x the diff pair via pitch
2 for TX traces and 2 for RX trace
No requirement
0.4
mm
Not allowed
0.075 / 0.2
uF
8
mm
USB and PCI Express
Notes
2.5GHz, half-rate architecture
Unidirectional, differential
To GND Single Ended for P and N
±15%. See Note 1
See Note 2
The following max length is
derived based on this
characteristic. See Note 3
Minimum width and spacing. 4x
or wider dielectric height spacing
is preferred
Max distance from BGA ball to
first PCB via.
Do trace length matching before
hitting discontinuities
Longer via stubs would require
review
Only required for TX when routed
to connector
Discontinuity such as edge finger,
component pad
DG-10141-001_v1.1 | 25
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