Nvidia Jetson TX2 NX Manual page 49

Parameter
The traces after main route via should be routed as 100Ω differential or as uncoupled 50ohm SE traces on PCB
top or bottom.
Max distance from R to main trace (seg B)
PD
Max distance from AC cap to RPD stubbing point (seg A)
Max distance between ESD and signal via
Add-on Components
Example of a case where space is limited for placing
components.
AC Cap
Value
Max via distance from BGA
Location
Placement
PTH design
Micro-via design
Void
Pull-down Resistor (R ), choke/FET
PD
Value
Location.
Layer of placement
Choke between R and FET
PD
choke
Max trace Rdc
Max trace length
Void
Common-mode Choke (Not recommended – only used if absolutely required for EMI issues)
See Appendix A for details on CMC if implemented.
ESD (On-chip protection diode can withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing option)
Max junction capacitance (IO to GND)
Footprint
Location
Void
Series Resistor (R ) – Series resistor on N/P path for HDMI 2.0 (mandatory)
S
Value
Location
Void
NVIDIA Jetson TX2 NX
Requirement Units
1 mm
~0 mm
3 mm
Top: See Figure 7-12
0.1
7.62 (52.5) mm (ps)
must be placed before pull-down resistor
Place cap on bottom layer if main-route
above core
Place cap on top layer if main-route below
core
Not Restricted
GND (or PWR) void under/above the cap is
needed. Void size = SMT area + 1x dielectric
height keepout distance
500
Must be placed after AC cap
Same layer as AC cap. The FET and choke
can be placed on the opposite layer thru a
PTH via
600 or Ω @ 100 MHz
1 uH@DC-100 MHz
≤20 mΩ
4 mm
GND/PWR void under/above cap is preferred
0.35
Pad right on the net instead of trace stub
After pull-down resistor/CMC and before R
GND/PWR void under/above the cap is
needed. Void size = 1mm x 2mm for 1 pair
≤ 6
After all components and before HDMI
connector
GND/PWR void under/above the R
dielectric height keepout distance.
Notes
Bottom: See Figure 7-13
uF
The distance between the AC cap and
the HDMI connector is not restricted.
See Figure 7-14
Ω
Placement: See Figure 7-15
Can be choke or Trace.
Recommended option for HDMI2.0
HF1-9 improvement.
pF e.g. Texas Instruments
TPD4E02B04DQAR
See Figure 7-16
S
See Figure 7-17
Ω ± 10%. 0ohm is acceptable if the
design passes the HDMI2.0 HF1-9
test. Otherwise, adjust the R
ensure the HDMI2.0 tests pass: Eye
diagram, Vlow test and HF1-9 TDR
test
device is needed. Void size = SMT area + 1x
S
DG-10141-001_v1.1 | 41
Display
value to
S