Figure 7-4. S-Parameter; Figure 7-5. Via Topology #1; Figure 7-6. Via Topology #2; Table 7-8. Edp And Dp Signal Connections - Nvidia Jetson TX2 NX Manual

The following figures show the eDP and DP interface signal routing requirements.
Figure 7-4. S-parameter
Figure 7-5. Via Topology #1
Figure 7-6. Via Topology #2
Table 7-8. eDP and DP Signal Connections
Module Pin Name Type
DPx_TXD[3:0]_N/P O
DPx_AUX_N/P I/OD
DPx_HPD I
NVIDIA Jetson TX2 NX
Termination
Series 0.1uF capacitors and ESD to GND on all.
Series 0.1uF capacitors. 100kΩ pulldown on
DP0_AUX_P and 100kΩ pull-up to VDD_3V3_SYS on
DP0_AUX_N. ESD to GND on both.
From module pin: 10kΩ pull-up to 1.8V, level shifter
and 100kΩ pulldown on connector side of shifter and
ESD to GND.
Description
eDP/DP Differential CLK/Data Lanes: Connect to
matching pins on display connector.
eDP/DP: Auxiliary Channels: Connect to AUX_CH-/+
on display connector.
eDP/DP: Hot Plug Detect: Connect to HPD pin on
display connector through level shifter.
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Display