Chapter 8. Mipi Csi Video Input; Table 8-1. Jetson Tx2 Nx Csi Pin Description - Nvidia Jetson TX2 NX Manual

Chapter 8. MIPI CSI Video Input

Jetson TX2 NX brings twelve MIPI CSI lanes to the connector. Three quad-lane camera
streams or two quad-lane plus two dual-lane camera streams or one quad-lane plus three
dual-lane camera streams are supported. Each data lane has a peak bandwidth of up to 2.5
Gbps.
Table 8-1. Jetson TX2 NX CSI Pin Description
Pin # Module Pin Name Tegra X2 Signal
10 CSI0_CLK_N CSI_A_CLK_N
12 CSI0_CLK_P CSI_A_CLK_P
4 CSI0_D0_N CSI_A_D0_N
6 CSI0_D0_P CSI_A_D0_P
16 CSI0_D1_N CSI_A_D1_N
18 CSI0_D1_P CSI_A_D1_P
9 CSI1_CLK_N CSI_B_CLK_N
11 CSI1_CLK_P CSI_B_CLK_P
3 CSI1_D0_N CSI_B_D0_N
5 CSI1_D0_P CSI_B_D0_P
15 CSI1_D1_N CSI_B_D1_N
17 CSI1_D1_P CSI_B_D1_P
28 CSI2_CLK_N CSI_C_CLK_N
30 CSI2_CLK_P CSI_C_CLK_P
22 CSI2_D0_N CSI_C_D0_N
24 CSI2_D0_P CSI_C_D0_P
34 CSI2_D1_N CSI_C_D1_N
36 CSI2_D1_P CSI_C_D1_P
27 CSI3_CLK_N CSI_D_CLK_N
29 CSI3_CLK_P CSI_D_CLK_P
21 CSI3_D0_N CSI_D_D0_N
23 CSI3_D0_P CSI_D_D0_P
33 CSI3_D1_N CSI_D_D1_N
35 CSI3_D1_P CSI_D_D1_P
52 CSI4_CLK_N CSI_E_CLK_N
54 CSI4_CLK_P CSI_E_CLK_P
46 CSI4_D0_N CSI_E_D0_N
48 CSI4_D0_P CSI_E_D0_P
58 CSI4_D1_N CSI_E_D1_N
60 CSI4_D1_P CSI_E_D1_P
NVIDIA Jetson TX2 NX
Usage/Description
Camera, CSI 0 Clock
Camera, CSI 0 Data 0
Camera, CSI 0 Data 1
Camera, CSI 1 Clock
Camera, CSI 1 Data 0
Camera, CSI 1 Data 1
Camera, CSI 2 Clock
Camera, CSI 2 Data 0
Camera, CSI 2 Data 1
Camera, CSI 3 Clock
Camera, CSI 3 Data 0
Camera, CSI 3 Data 1
Camera, CSI 4 Clock
Camera, CSI 4 Data 0
Camera, CSI 4 Data 1
Usage on DevKit
Direction Pin Type
Carrier Board
Camera Connector #1
Not Assigned
Camera Connector #2 Input
Not Assigned
DG-10141-001_v1.1 | 46
MIPI D-PHY