Mipi Dsi And Csi Design Guidelines; Figure 7-1. Dsi 1 X 2 Lane Connection Example; Table 7-3. Mipi Dsi And Csi Interface Signal Routing Requirements - Nvidia Jetson TX2 NX Manual

Figure 7-1. DSI 1 x 2 Lane Connection Example
Jetson
Tegra
DSI_A_CLK_P
DSI/CSI
DSI_A_CLK_N
DSI_A_D0_P
DSI_A_D0_N
DSI_A_D1_P
DSI_A_D1_N
SYS
LCD_BL_PWM
Note: If EMI/ESD devices are necessary, they must be tuned to minimize impact to signal quality,
which must meet the DSI spec. requirements for the frequencies supported by the design.
7.1.1

MIPI DSI and CSI Design Guidelines

Table 7-3 details the MIPI DSI and CSI interface signal routing requirements.
Table 7-3. MIPI DSI and CSI Interface Signal Routing Requirements
Parameter
Max frequency/data rate (per data lane)
DSI
CSI
Number of loads
Reference plane
Trace impedance (Diff pair / SE)
Via proximity (signal to reference)
Intra-pair trace spacing
Inter-pair trace spacing (Microstrip / Stripline)
Max PCB breakout length
Insertion Loss
1 Gbps
1.5 Gbps
2.5 Gbps
Max trace delay
1 Gbps
1.5 Gbps
2.5 Gbps
Max intra-pair skew
NVIDIA Jetson TX2 NX
DSI_CLK_P
78
DSI_CLK_N
76
DSI_D0_P
72
DSI_D0_N
70
DSI_D1_P
84
DSI_D1_N
82
GPIO07
Optional Backlight PWM
206
Requirement
750 / 1500
1250 / 2500
1
GND
90-100 / 45-50
< 0.65 (3.8)
0.15mm
4x / 3x
5
3.0
2.9
1.92
421 (2526)
319 (1913)
150 (900)
1
Display
Connector (DSI)
CLKP
CLKN
D0P
D0N
D1P
D1N
Units Notes
MHz/Mbps
load
Ω ±10%
mm (ps)
mm Can be adjusted to meet
Differential Impedance. Loosely
Coupled Diff. Pair
recommended by Spec.
dielectric
mm
dB
mm (ps)
ps
DG-10141-001_v1.1 | 31
Display