Figure 6-7. Example Pcie Connections - Nvidia Jetson TX2 NX Manual

Figure 6-7. Example PCIe Connections
Jetson
Tegra - PCIe
PEX
PEX_TX2N
PEX_TX2P
PEX_RX2N
PEX_RX2P
PEX_TX4N
PEX_TX4P
PEX_RX4N
PEX_RX4P
PEX_CLK1_N
PEX_CLK1_P
PEX_TX0N
PEX_TX0P
PEX_RX0N
PEX_RX0P
PEX_CLK3_N
PEX_CLK3_P
PEX
PEX_L0_CLKREQ_N
PEX_L0_RST_N
Control
PEX_L2_CLKREQ_N
PEX_L2_RST_N
PEX_WAKE_N
VDD_3V3_SYS
Notes:
1. AC Capacitors required on RX lines on carrier board if connected directly to device. Not
needed if connected to PCIe connector, M.2 Key M, etc. In those cases, the AC caps are on the
board plugged into those connectors.
2. See design guidelines for correct AC capacitor values.
3. The PCIe clock outputs comply to the PCIe CEM specification "REFCLK DC Specifications and
AC Timing Requirements." The clocks are HCSL compatible as are the RX/TX signals.
NVIDIA Jetson TX2 NX
See Note 1
PCIE0_TX1_N
140
PCIE0_TX1_P
142
PCIE0_RX1_N
137
PCIE0_RX1_P
139
PCIE0_TX0_N
134
PCIE0_TX0_P
136
PCIE0_RX0_N
131
PCIE0_RX0_P
133
PCIE0_CLK_N
160
PCIE0_CLK_P
162
(PCIE1_TX0_N) RSVD
172
(PCIE1_TX0_P) RSVD
174
(PCIE1_RX0_N) RSVD
167
(PCIE1_RX0_P) RSVD
169
(PCIE1_CLK_N) RSVD
173
(PCIE1_CLK_P) RSVD
175
PCIE0_CLKREQ*
180
PCIE0_RST*
181
(PCIE1_CLKREQ*) RSVD
182
(PCIE1_RST *) RSVD
183
PCIE_WAKE*
179
USB and PCI Express
PCIe 0 Lane 1
PCIe 0
(x2 - Ctrl #0)
PCIe 0 Lane 0
PCIe 1
(x1 - Ctrl #2)
PCIe 0
(x2 - Ctrl #0)
PCIe 1
(x1 - Ctrl #2)
Shared
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