Figure 6-8. Ac Cap Voiding; Table 6-10. Pcie Signal Connections - Nvidia Jetson TX2 NX Manual

Parameter
Voiding
General: See Chapter 15 for guidelines related to serpentine routing, routing over voids and noise coupling
Notes:
1. The PCIe spec. has 40-60Ω absolute min/max trace impedance, which can be used instead of the 50Ω, ± 15%.
2. If routing in the same layer is necessary, route group TX and RX separately without mixing RX/TX routes and keep distance between
nearest TX/RX trace and RX to other signals 3x RX-RX separation.
3. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace
lengths will need to be reduced.
4. Do length matching before via transitions to different layers or any discontinuity to minimize common mode conversion.
Figure 6-8. AC Cap Voiding
Table 6-10. PCIe Signal Connections
Module Pin Name
(Jetson TX2 NX Function)
PCIe Interface 0 (x2 – Controller #0)
PCIE0_TX1_N/P - Lane 1
PCIE0_TX0_N/P - Lane 0
PCIE0_RX1_N/P - Lane 1
PCIE0_RX0_N/P - Lane 0
PCIE0_CLK_N/P
PCIE0_CLKREQ*
PCIE0_RST*
PCIe Interface 1 (x1 – Controller #2)
PCIE1_TX0_N/P
PCIE1_RX0_N/P
PCIE1_CLK_N/P
NVIDIA Jetson TX2 NX
Requirement
Voiding the plane directly under the pad
3-4 mils larger than the pad size is
recommended.
Type Termination
DIFF Series 0.1uF Capacitor
OUT
DIFF IN Series 0.1uF capacitors
near Jetson TX2 NX pins or
device if device on main
PCB.
DIFF
OUT
I 47kΩ pull-up to
VDD_3V3_SYS on module
O 4.7kΩ pull-up to
VDD_3V3_SYS on module
DIFF Series 0.1uF Capacitor
OUT
DIFF IN Series 0.1uF capacitors
near Jetson TX2 NX pins or
device if device on main
PCB.
DIFF
OUT
USB and PCI Express
Units Notes
See Figure 6-8
Description
Differential Transmit Data Pairs: Connect to TX_N/P pins of
PCIe connector or RX_N/P pin of PCIe device through AC cap
according to supported configuration.
Differential Receive Data Pairs: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap
according to supported configuration.
Differential Reference Clock Output: Connect to
REFCLK_N/P pins of PCIe device/connector
PCIe Clock Request for PCIE0_CLK: Connect to CLKREQ pins
on device/connector(s)
PCIe Reset: Connect to PERST pins on device/connector(s)
Differential Transmit Data Pair: Connect to TX_N/P pins of PCIe
connector or RX_N/P pin of PCIe device through AC cap
according to supported configuration.
Differential Receive Data Pair: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap
according to supported configuration.
Differential Reference Clock Output: Connect to
REFCLK_N/P pins of PCIe device/connector
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