Figure 7-9. Pcie Root Port Connections Example - Nvidia Jetson Orin NX Design Manual

Figure 7-9. PCIe Root Port Connections Example
SoC - PCIe
UPHY0
HS_UPHY0_L7_TX_N/P
HS_UPHY0_L7_RX_N/P
HS_UPHY0_L6_TX_N/P
HS_UPHY0_L6_RX_N/P
HS_UPHY0_L5_TX_N/P
HS_UPHY0_L5_RX_N/P
HS_UPHY0_L4_TX_N/P
HS_UPHY0_L4_RX_N/P
HS_UPHY0_REFCLK2_N/P
SF_PCIE4_CLK_N/P
See Note 1
HS_UPHY0_L3_TX_N/P
HS_UPHY0_L3_RX_N/P
SF_PCIE1_CLK_N/P
UPHY2
HS_UPHY2_L1_TX_N/P
HS_UPHY2_L1_RX_N/P
HS_UPHY2_L0_TX_N/P
HS_UPHY2_L0_RX_N/P
SF_PCIE7_CLK_N/P
SF_PCIE9_CLK_N
SF_PCIE9_CLK_P
PEX
GP183_PCIE4_CLKREQ_N
Ctrl GP184_PCIE4_RST_N
GP177_PCIE1_CLKREQ_N
GP178_PCIE1_RST_N
GP187_PCIE7_CLKREQ_N
GP188_PCIE7_RST_N
GP191_PCIE9_CLKREQ_N
GP192_PCIE9_RST_N
GP185_PCIE_WAKE_N
GP21
Notes:
1. For Root Port operation, the mux should be set to output the SF_PCIE10_CLK signals. SoC
GP21 which is used for the mux select should be set low.
2. AC Capacitors required on RX lines on carrier board if connected directly to device. They
should not be on the carrier board if connected to PCIe connector, M.2 Key M, etc. In those
cases, the AC caps are on the board connected to those connectors.
3. See design guidelines for correct AC capacitor values.
4. The PCIe REFCLK inputs and CLK outputs comply to the PCIe CEM specification "REFCLK DC
Specifications and AC Timing Requirements." The clocks are HCSL compatible.
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Jetson
PCIE0_TX3_N/P
154/156
PCIE0_RX3_N/P
155/157
PCIE0_TX2_N/P
148/150
PCIE0_RX2_N/P
149/151
PCIE0_TX1_N/P
140/142
PCIE0_RX1_N/P
137/139
PCIE0_TX0_N/P
134/136
PCIE0_RX0_N/P
131/133
PCIE0_CLK_N/P
160/162
Mux
GP21
SEL
PCIE1_TX0_N/P
172/174
PCIE1_RX0_N/P
167/169
PCIE1_CLK_N/P
173/175
CSI4_D3_N/P
CSI4_D1_N/P
CSI4_D0_N/P
CSI4_D2_N/P
CSI4_CLK_N/P
SDMMC_CMD
SDMMC_CLK
3.3V
PCIE0_CLKREQ*
PCIE0_RST*
PCIE1_CLKREQ*
PCIE1_RST*
3.3V
SDMMC_DAT1
SDMMC_DAT0
SDMMC_DAT3
SDMMC_DAT2
PCIE_WAKE*
HS_UPHY0 _REFCLK2/
SF_PCIE4_CLK Mux Control
See Note 2
PCIe 0 Lane 3
PCIe 0 Lane 2
PCIe 0 Lane 1
PCIe 0 Lane 0
PCIE2_TX1_N/P
64/66
PCIe 1 L1
PCIE2_RX1_N/P
58/60
PCIE2_TX0_N/P
46/48
PCIe 1 L0
PCIE2_RX0_N/P
40/42
PCIE2_CLK_N/P
52/54
PCIE3_CLK_N
227
PCIE3_CLK_P
229
180
181
182
183
PCIE2_CLKREQ*
221
PCIE2_RST*
219
PCIE3_CLKREQ*
225
PCIE3_RST*
223
Shared wake pin
179
USB and PCIe
PCIe 0 (Ctrl #4) –
PCIe x4 conn/device
(i.e. M.2 Key M)
PCIe 1 (Ctrl #1) –
PCIe x1 conn/device
(i.e. M.2 Key E)
PCIe 2 (Ctrl #7) –
PCIe x2
Or
PCIe 2 (Ctrl #7) –
PCIe x1 (Lane 0) and
PCIe 3 (Ctrl #9) –
PCIe x1 (Lane 1)
PCIe 0 (Ctrl #4) –
PCIe x4 conn/device
(i.e. M.2 Key M)
PCIe 1 (Ctrl #1) –
PCIe x1 conn/device
(i.e. M.2 Key E)
PCIe 2 (Ctrl #7) –
PCIe x2 or x1)
PCIe 3 (Ctrl #9) –
PCIe x1)
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