Samsung S3P80C5 User Manual page 97

INTERRUPT STRUCTURE
Vector Address
Decimal
Value Value
254 100H
252
250
246
244
236
232
232
232
232
230
228
226
224
NOTES:
1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
5-6
Table 5-1. S3P80C5/C80C5/C80C8 Interrupt Vectors
Interrupt Source
Hex
Basic timer overflow
FCH Timer 0 (match)
FAH Timer 0 overflow
F6H Timer 1 (match)
F4H Timer 1 overflow
ECH Counter A
E8H P0.7 external interrupt
E8H P0.6 external interrupt
E8H P0.5 external interrupt
E8H P0.4 external interrupt
E6H P0.3 external interrupt
E4H P0.2 external interrupt
E2H P0.1 external interrupt
E0H P0.0 external interrupt
S3P80C5/C80C5/C80C8
Request
Interrupt Priority in
Level Level
RESET
–
IRQ0 1
0
IRQ1 1
0
IRQ4 –
IRQ7 –
–
–
–
IRQ6 3
2
1
0
Reset/Clear
H/W S/W
√
√
√
√
√
√
√
√
√
√
√
√
√
√