Samsung S3P80C5 User Manual page 94

S3P80C5/C80C5/C80C8
S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE
The S3P80C5 microcontroller supports two kinds interrupt structure
— Vectored Interrupt
— Non vectored interrupt (Reset interrupt): INTR
The S3P80C5/C80C5/C80C8 microcontroller supports thirteen interrupt sources. Nine of the interrupt sources
have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector
address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in
Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first. (The relative priorities of multiple interrupts within a
single level are fixed in hardware.)
When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the
program counter value and state flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed. The S3P80C5/C80C5/C80C8 microcontroller supports non vectored interrupt -
Interrupt with Reset(INTR) - to occur interrupt with system reset. The Interrupt with Reset(INTR) has nothing to do
with interrupt levels, vectors and the registers that are related to interrupt setting. It occurs only according to the
"P0" during " STOP " regardless any other things. Namely, only when a falling/rising edge occurs at any pin of
Port 0 during STOP status, this INTR and a system reset occurs even though SYM.0 is "0"(Disable interrupt). But
it dose not occurs while the oscillation - "IDLE" or "OPERATING" status- even though a falling/rising edge occurs
at port 0.
Following is the sequence that occurs Interrupt with Reset(INTR).
1. The oscillation status is "freeze" : STOP mode
2. A falling/rising edge is detected to any pin of Port 0.
3. INTR occurs and it makes system reset.
4. STOP mode is released by this system reset.
Because H/W reset occurs whenever INTR occurs. A user should aware of the each ports, system
register, control register etc."
NOTE
INTERRUPT STRUCTURE
5-3