Samsung S3P80C5 User Manual page 199

CLOCK CIRCUITS
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by Power On
Reset operation or by a non-vectored interrupt - interrupt with reset (INTR). To enter the Stop mode,
STOPCON (STOP Control register) has to be loaded with value, #0A5H before STOP instruction execution.
After recovering from the Stop mode by reset or interrupt, STOPCON register is automatically cleared.
— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the
interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (external or
internally generated).
NOTES:
1.
2.
7-2
STOP
STOPCON
Instruction
Oscillator
Stop
Main
OSC
Oscillator
Wake-up
Noise
filter
(1)
INT Pin
An external interrupt with an RC-delay noise filter (for S3C80C5/C80C8/,
INT0-4) is fiexed to release Stop mode and "wake up" the main
oscillator.
Because the S3C80C5/C80C8 has no subsystem clock, the 3-bit CLKCON
signature code (CLKCON.2-CLKCON.0) is no meaning.
Figure 7-3. System Clock Circuit Diagram
CLKCON.3,.4
1/2
M
U
X
1/8
1/16
S3P80C5/C80C5/C80C8
CPU
Clock