Samsung S3P80C5 User Manual page 217

I/O PORTS
9-6
Port 0 Interrup Enable Register (P0INT)
MSB .7 .6
P0.6/INT4
P0.7/INT4 P0.5/INT4
Port 0 Interrupt Enable Bits:
0 Disable interrupt
1 Enable interrupt
Figure 9-5. Port 0 External Interrupt Control Register (P0INT)
Port 0 Interrup Pending Register (P0PND)
MSB .7 .6
P0.6/INT4
P0.7/INT4 P0.5/INT4
Port 0 Interrupt Pending Bits:
0 Interrupt not pending
0 Clear P0.n pending condition (when write)
1 P0.n interrupt is pending
1 No effect (when write)
Figure 9-6. Port 0 External Interrupt Pending Register (P0PND)
F1H, Set 1, R/W
.5 .4 .3 .2
P0.4/INT4 P0.2/INT2
P0.3/INT3 P0.1/INT1
F2H, Set 1, R/W
.5 .4 .3 .2
P0.4/INT4 P0.2/INT2
P0.3/INT3 P0.1/INT1
S3P80C5/C80C5/C80C8
.1 .0 LSB
P0.0/INT0
.1 .0 LSB
P0.0/INT0