System Mode Register (Sym) - Samsung S3P80C5 User Manual

INTERRUPT STRUCTURE

SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2,
is undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which
follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to
enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this
purpose.
External interface
tri-state enable bit:
0 = Normal (Tri-state)
1 = High (Tri-state)
Not used for the S3C80C5/C80C8.
5-10
System Mode Register (SYM)
.7 .6 .5
MSB
NOTE: An external memory interface is not implemented.
Figure 5-5. System Mode Register (SYM)
DEH, Set 1, R/W
.4 .3 .2
Fast interrupt level
selection bits:
0 0 0 IRQ0
0 0 1 IRQ1
0 1 0 Not used
0 1 1 Not used
1 0 0 Not used
1 0 1 Not used
1 1 0 IRQ6
1 1 1 IRQ7
S3P80C5/C80C5/C80C8
.1 .0
LSB
Global interrupt enable bit:
0 = Disable all interrupts
1 = Enable all interrupts
Fast interrupt enable bit:
0 = Disable fast interrupt
1 = Enable fast interrupt