Samsung S3C80M4/F80M4 User Manual
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Samsung S3C80M4/F80M4 User Manual

Samsung S3C80M4/F80M4 User Manual

8-bit cmos microcontrollers
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S3C80M4/F80M4
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1

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Summary of Contents for Samsung S3C80M4/F80M4

  • Page 1 S3C80M4/F80M4 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1...
  • Page 2 Samsung reserves the right to make changes in its intended for surgical implant into the body, for other products or product specifications with the intent to...
  • Page 3 Chapter 16 Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C80M4/F80M4 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

  • Page 4: Table Of Contents

    Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers ........................1-1 S3C80M4/F80M4 Microcontroller .........................1-1 Flash................................1-1 Features ................................1-2 Block Diagram ...............................1-3 Pin Assignment .............................1-4 Pin Descriptions ............................1-6 Pin Circuits ..............................1-7 Chapter 2 Address Spaces Overview................................2-1 Program Memory (ROM)..........................2-2 Register Architecture.............................2-3...
  • Page 5 Fast Interrupt Processing........................5-16 Chapter 6 Instruction Set Overview ............................... 6-1 Data Types............................6-1 Register Addressing..........................6-1 Addressing Modes ..........................6-1 Flags Register (FLAGS)........................6-6 Flag Descriptions ..........................6-7 Instruction Set Notation........................6-8 Condition Codes ..........................6-12 Instruction Descriptions........................6-13 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 6 Stop Mode ............................8-4 Idle Mode ..............................8-5 Chapter 9 I/O Ports Overview................................9-1 Port Data Registers ..........................9-1 Port 0 ..............................9-2 Port 1 ..............................9-5 Chapter 10 Basic Timer Overview................................10-1 Basic Timer (BT)...........................10-1 Basic Timer Control Register (BTCON) ....................10-1 Basic Timer Function Description......................10-3 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 7 Overview ............................... 16-1 SHINE ..............................16-1 SAMA Assembler ..........................16-1 SASM88 ............................... 16-1 HEX2ROM ............................16-1 Target Boards ............................16-1 TB80M4 Target Board ......................... 16-3 SMDS2+ Selection (SAM8) ......................... 16-5 Idle LED ............................... 16-5 Stop LED.............................. 16-5 viii S3C80M4/F80M4 MICROCONTROLLER...
  • Page 8 Figure Title Page Number Number Block Diagram ......................1-3 S3C80M4/F80M4 Pin Assignments (20-DIP-300A, 20-SOP-375)......1-4 S3C80M4/F80M4 Pin Assignments (16-DIP-300A, 16-SOP-375)......1-5 Pin Circuit Type A.......................1-7 Pin Circuit Type B.......................1-7 Pin Circuit Type E-2 (P1.4–P1.6) ................1-7 Pin Circuit Type D-4 (P0)....................1-8 Pin Circuit Type E-4 (P1.0–P1.3) ................1-8 Program Memory Address Space ................2-2...
  • Page 9 Page Number Number Register Description Format ..................4-3 S3C8-Series Interrupt Types ..................5-2 S3C80M4/F80M4 Interrupt Structure................. 5-3 ROM Vector Address Area ..................5-4 Interrupt Function Diagram ..................5-7 System Mode Register (SYM) ................... 5-9 Interrupt Mask Register (IMR) ................... 5-10 Interrupt Request Priority Groups ................
  • Page 10 S3F80M4 Pin Assignments (20-DIP-300A, 20-SOP-375) .........15-2 15-2 S3F80M4 Pin Assignments (16-DIP-300A, 16-SOP-375) .........15-3 15-3 Operating Voltage Range ...................15-6 16-1 SMDS Product Configuration (SMDS2+) ..............16-2 16-2 TB80M4 Target Board Configuration .................16-3 16-3 20-Pin Connectors (J101) for TB80M4...............16-7 16-4 S3E80M0 Cables for 16/20-DIP Package ..............16-7 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 11 Instruction Notation Conventions ................6-9 Opcode Quick Reference ...................6-10 Condition Codes ......................6-12 S3C80M4/F80M4 Set 1 Register and Values after RESET ........8-2 S3C80M4/F80M4 Set 1, Bank 0 Register and Values after RESET......8-3 S3C80M4/F80M4 Port Configuration Overview ............9-1 Port Data Register Summary..................9-1 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 12 Main-clock Selection Settings for TB80M4..............16-4 16-3 Device Selection Settings for TB80M4 ..............16-5 16-4 The SMDS2+ Tool Selection Setting ................. 16-5 16-5 Smart Option Source Selection Settings for TB80M4 ..........16-6 16-6 Smart Option Switch Setting for TB80M4 ..............16-6 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 13 Setting the Register Pointers ........................2-9 Using the RPs to Calculate the Sum of a Series of Registers..............2-10 Addressing the Common Working Register Area..................2-14 Standard Stack Operations Using PUSH and POP..................2-19 Chapter 7: Clock Circuit How to Use Stop Instruction ........................7-6 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 14 Register Pointer 0....................... 4-21 Register Pointer 1....................... 4-21 Stack Pointer (High Byte) ................... 4-22 Stack Pointer (Low Byte).................... 4-22 STPCON Stop Control Register ....................4-23 System Mode Register ....................4-24 T0CON Timer 0 Control Register .................... 4-25 S3C80M4/F80M4 MICROCONTROLLER xvii...
  • Page 15 Enable Interrupts ......................6-40 ENTER Enter ........................... 6-41 EXIT Exit..........................6-42 IDLE Idle Operation......................6-43 Increment ........................6-44 INCW Increment Word......................6-45 IRET Interrupt Return ......................6-46 Jump........................... 6-47 Jump Relative......................6-48 Load..........................6-49 Load Bit ........................6-51 S3C80M4/F80M4 MICROCONTROLLER...
  • Page 16 Subtract with Carry .....................6-77 Set Carry Flag......................6-78 Shift Right Arithmetic ....................6-79 SRP/SRP0/SRP1 Set Register Pointer....................6-80 STOP Stop Operation......................6-81 Subtract ........................6-82 SWAP Swap Nibbles......................6-83 Test Complement under Mask ...................6-84 Test under Mask ......................6-85 Wait for Interrupt ......................6-86 Logical Exclusive OR....................6-87 S3C80M4/F80M4 MICROCONTROLLER...

  • Page 17: Chapter 1 Product Overview

    PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture —...

  • Page 18: Features

    PRODUCT OVERVIEW S3C80M4/F80M4 FEATURES Two Power-Down Modes • SAM88 RC CPU core • Idle: only CPU clock stops • Stop: selected system clock and CPU clock stop Memory • Program Memory (ROM) Power Consumption - 4K × 8 bits program memory •...

  • Page 19: Block Diagram

    S3C80M4/F80M4 PRODUCT OVERVIEW BLOCK DIAGRAM nRESET Watchdog Timer OSC. Basic Timer Port I/O and Interrupt Control P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 I/O Port 0 P0.4 T0OUT/P1.0 8-Bit Timer/ P0.5 SAM88RC CPU Counter 0 T0CLK/P1.1 P0.6/PWM P0.7 P1.0/T0OUT P1.1/T0CLK 4-Kbyte 128-byte P1.2 Register File PWM/P0.6...

  • Page 20: Pin Assignment

    PRODUCT OVERVIEW S3C80M4/F80M4 PIN ASSIGNMENT P0.0/INT0 P0.1/INT1 nRESET P0.2/INT2 S3C80M4/F80M4 (20-DIP-300A) P1.0/T0OUT P0.3/INT3 (20-SOP-375) P1.1/T0CLK P0.4 P1.2 P0.5 P1.3 P0.6/PWM P1.4 P0.7 P1.5 P1.6/CLKOUT Figure 1-2. S3C80M4/F80M4 Pin Assignments (20-DIP-300A, 20-SOP-375)
  • Page 21 S3C80M4/F80M4 PRODUCT OVERVIEW P0.0/INT0 P0.1/INT1 nRESET P0.2/INT2 S3C80M4/F80M4 (16-DIP-300A) P1.0/T0OUT P0.3/INT3 (16-SOP-375) P1.1/T0CLK P0.4 P1.2 P0.5 P1.3 P0.6/PWM Figure 1-3. S3C80M4/F80M4 Pin Assignments (16-DIP-300A, 16-SOP-375)

  • Page 22: Pin Descriptions

    PRODUCT OVERVIEW S3C80M4/F80M4 PIN DESCRIPTIONS Table 1-1. S3C80M4/F80M4 Pin Descriptions Pin Description Circuit Share (note) Names Type Type Pins Numbers P0.0–P0.7 I/O port with bit-programmable pins; 19–13 INT0–INT3 Schmitt trigger input or push-pull output and (15–9) software assignable pull-ups. Alternately used for external interrupt input (noise filters, interrupt enable and pending control).

  • Page 23: Pin Circuits

    S3C80M4/F80M4 PRODUCT OVERVIEW PIN CIRCUITS P-Channel Schmitt Trigger N-Channel Figure 1-4. Pin Circuit Type A Figure 1-5. Pin Circuit Type B Open drain Pull-up Enable Resistor Pull-up Enable P-CH Data N-CH Output Disable Figure 1-6. Pin Circuit Type E-2 (P1.4–P1.6)
  • Page 24 PRODUCT OVERVIEW S3C80M4/F80M4 Pull-up Resistor Pull-up Enable P-CH Data Output N-CH Disable Figure 1-7. Pin Circuit Type D-4 (P0) Open drain Pull-up Enable Resistor Resistor Enable P-CH Data N-CH Output Disable Schmitt Trigger Figure 1-8. Pin Circuit Type E-4 (P1.0-P1.3)

  • Page 25: Chapter 2 Address Spaces

    S3C80M4/F80M4 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C80M4 microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file.

  • Page 26: Program Memory (Rom)

    S3C80M4/F80M4 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C80M4/F80M4 has 4K bytes internal mask- programmable program memory. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory.

  • Page 27: Register Architecture

    1), and the lower 32-byte area is a single 32-byte common area. In case of S3C80M4/F80M4 the total number of addressable 8-bit registers is 175. Of these 175 registers, 13 bytes are for CPU and system control registers, 18 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 128 registers are for general-purpose use, page 0.
  • Page 28 ADDRESS SPACES S3C80M4/F80M4 Set1 Peripheral Control Registers (Register Addressing Mode) Page 0 Bytes System Control Registers (Register Addressing Mode) General Purpose Working Registers Register Files (Register Addressing Mode) (All Addressing Modes) Bytes Figure 2-2. Internal Register File Organization...

  • Page 29: Register Page Pointer (Pp)

    S3C80M4/F80M4 ADDRESS SPACES REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH).

  • Page 30: Register Set 1

    ADDRESS SPACES S3C80M4/F80M4 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1.

  • Page 31: Prime Register Space

    S3C80M4/F80M4 ADDRESS SPACES PRIME REGISTER SPACE The lower 128 bytes (00H–7FH) of the S3C80M4's one 128-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area is immediately addressable following a reset.

  • Page 32: Working Registers

    ADDRESS SPACES S3C80M4/F80M4 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices."...

  • Page 33: Using The Register Points

    S3C80M4/F80M4 ADDRESS SPACES USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
  • Page 34 ADDRESS SPACES S3C80M4/F80M4 F7H (R7) 8-Byte Slice F0H (R0) 16-Byte Register File Contiguous Contains 32 1 1 1 1 0 X X X working 8-Byte Slices Register block 7H (R15) 0 0 0 0 0 X X X 8-Byte Slice 0H (R0) Figure 2-7.

  • Page 35: Register Addressing

    S3C80M4/F80M4 ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
  • Page 36 ADDRESS SPACES S3C80M4/F80M4 Special-Purpose Registers General-Purpose Register Bank 1 Bank 0 Control (Not used for Registers the S3C80M4) Set 2 System (Not used for Registers the S3C80M4) Register Pointers Each register pointer (RP) can independently point Prime to one of the 24 8-byte "slices" of the register file Registers (other than set 2).

  • Page 37: Common Working Register Area (C0H-Cfh)

    S3C80M4/F80M4 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area.

  • Page 38: 4-Bit Working Register Addressing

    ADDRESS SPACES S3C80M4/F80M4 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. 1. LD 0C2H,40H ; Invalid addressing mode!
  • Page 39 S3C80M4/F80M4 ADDRESS SPACES Selects RP0 or RP1 Address OPCODE 4-bit address Register pointer provides three provides five low-order bits high-order bits Together they create an 8-bit register address Figure 2-11. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0...

  • Page 40: 8-Bit Working Register Addressing

    ADDRESS SPACES S3C80M4/F80M4 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B."...
  • Page 41 S3C80M4/F80M4 ADDRESS SPACES 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 Selects RP1 8-bit address Register form instruction 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1...

  • Page 42: System And User Stack

    SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C80M4/F80M4 architecture supports stack operations in the internal register file.
  • Page 43 S3C80M4/F80M4 ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SPL ← FFH SPL,#0FFH ; (Normally, the SPL is set to 0FFH by the initialization ;...
  • Page 44 ADDRESS SPACES S3C80M4/F80M4 NOTES 2-20...
  • Page 45 S3C80M4/F80M4 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
  • Page 46 ADDRESSING MODES S3C80M4/F80M4 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
  • Page 47 S3C80M4/F80M4 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
  • Page 48 ADDRESSING MODES S3C80M4/F80M4 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory REGISTER Example PAIR Instruction Points to References OPCODE Register Pair Program 16-Bit Memory Address Points to Program Program Memory Memory Sample Instructions: Value used in OPERAND Instruction CALL...
  • Page 49 S3C80M4/F80M4 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points Program Memory to start fo working register 4-bit block 3 LSBs Working Register Point to the OPCODE ADDRESS...
  • Page 50 ADDRESSING MODES S3C80M4/F80M4 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register 4-bit Working block Register Address Register Next 2-bit Point Pair OPCODE...
  • Page 51 S3C80M4/F80M4 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
  • Page 52 ADDRESSING MODES S3C80M4/F80M4 INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working Program Memory register block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address Point to Working...
  • Page 53 S3C80M4/F80M4 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of Program Memory working register OFFSET block OFFSET NEXT 2 Bits 4-bit Working dst/src Register Register Address...
  • Page 54 ADDRESSING MODES S3C80M4/F80M4 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
  • Page 55 S3C80M4/F80M4 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: C,JOB1 Where JOB1 is a 16-bit immediate address CALL DISPLAY Where DISPLAY is a 16-bit immediate address Figure 3-11.
  • Page 56 ADDRESSING MODES S3C80M4/F80M4 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
  • Page 57 S3C80M4/F80M4 ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.
  • Page 58 ADDRESSING MODES S3C80M4/F80M4 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers.
  • Page 59 S3C80M4/F80M4 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C80M4 control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.
  • Page 60 CONTROL REGISTERS S3C80M4/F80M4 Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Port 0 Data Register Port 1 Data Register Location E2H is not mapped. Clock Output Control Register CLOCON Timer 0 Counter Register T0CNT Timer 0 Data Register...

  • Page 61: Flags System Flags Register

    S3C80M4/F80M4 CONTROL REGISTER Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or related bits Register location Register address in the internal register file Register ID Full Register name (hexadecimal) FLAGS - System Flags Register...
  • Page 62 CONTROL REGISTERS S3C80M4/F80M4 BTCON — Basic Timer Control Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) Disable watchdog timer function Others Enable watchdog timer function .3–.2...
  • Page 63 S3C80M4/F80M4 CONTROL REGISTER CLKCON — System Clock Control Register Set 1 Bit Identifier RESET Value – – – – – – – – – – Read/Write Addressing Mode Register addressing mode only Oscillator IRQ Wake-up Function Bit Enable IRQ for main wake-up in power down mode Disable IRQ for main wake-up in power down mode .6–.5...
  • Page 64 CONTROL REGISTERS S3C80M4/F80M4 CLOCON — Clock Output Control Register Set 1, Bank0 Bit Identifier RESET Value – – – – – – – – – – – – Read/Write Addressing Mode Register addressing mode only Not used for the S3C80M4 .7–.2...
  • Page 65 S3C80M4/F80M4 CONTROL REGISTER FLAGS — System Flags Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Carry Flag (C) Operation does not generate a carry or borrow condition Operation generates a carry-out or borrow into high-order bit 7...

  • Page 66: Imr Interrupt Mask Register

    CONTROL REGISTERS S3C80M4/F80M4 — Interrupt Mask Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.3 Disable (mask) Enable (unmask) Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.2...

  • Page 67: Iph Instruction Pointer (High Byte)

    S3C80M4/F80M4 CONTROL REGISTER — Instruction Pointer (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).

  • Page 68: Ipr Interrupt Priority Register

    CONTROL REGISTERS S3C80M4/F80M4 — Interrupt Priority Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C Group priority undefined B > C > A A >...

  • Page 69: Irq Interrupt Request Register

    S3C80M4/F80M4 CONTROL REGISTER — Interrupt Request Register Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.3 Not pending Pending Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.2...
  • Page 70 CONTROL REGISTERS S3C80M4/F80M4 P0CONH — Port 0 Control Register (High Byte) Set 1,Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.7 Schmitt trigger input mode Schmitt trigger input mode with pull-up resistor Not available Output mode, push-pull .5–.4...
  • Page 71 S3C80M4/F80M4 CONTROL REGISTER P0CONL — Port 0 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/INT3 Schmitt trigger input mode Schmitt trigger input mode with pull-up resistor Not available Output mode, push-pull .5–.4...
  • Page 72 CONTROL REGISTERS S3C80M4/F80M4 P0INT — Port 0 Interrupt Control Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P0.3/External interrupt (INT3) Enable Bits Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge .5–.4...
  • Page 73 S3C80M4/F80M4 CONTROL REGISTER P0PND — Port 0 Interrupt Pending Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.4 Not used for the S3C80M4 P0.3/External Interrupt (INT3) Pending Bit Interrupt request is not pending (When read), Clear pending bit when write 0 P0.3/INT3 interrupt request is pending (when read)
  • Page 74 CONTROL REGISTERS S3C80M4/F80M4 P1CONH — Port 1 Control Register (High Byte) Set 1, Bank 0 Bit Identifier RESET Value – – – – Read/Write Addressing Mode Register addressing mode only .7–.6 Not used for the S3C80M4 .5–.4 P1.6/CLKOUT Input mode...
  • Page 75 S3C80M4/F80M4 CONTROL REGISTER P1CONL — Port 1 Control Register (Low Byte) Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 P1.3 Schmitt trigger input mode Output mode, N-channel open-drain Not available Output mode, push-pull .5–.4...
  • Page 76 CONTROL REGISTERS S3C80M4/F80M4 P1PUR — Port 1 Pull-up Resistor Enable Register Set 1, Bank 0 Bit Identifier RESET Value – – Read/Write Addressing Mode Register addressing mode only Not used for the S3C80M4 P1.6 Pull-up Resistor Enable Bit Pull-up disable Pull-up enable P1.5 Pull-up Resistor Enable Bit...

  • Page 77: Pp Register

    S3C80M4/F80M4 CONTROL REGISTER — Register Page Pointer Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.4 Destination Register Page Selection Bits Destination: page 0 Others Not used for the S3C80M4 .3– .0 Source Register Page Selection Bits...
  • Page 78 CONTROL REGISTERS S3C80M4/F80M4 PWMCON — Pulse Width Modulation Control Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.6 PWM Input Clock Selection Bits fosc/64 fosc/8 fosc/2 fosc/1 Not used, But you must keep "1"...

  • Page 79: Rp0 Register Pointer 0

    S3C80M4/F80M4 CONTROL REGISTER — Register Pointer 0 Set 1 Bit Identifier RESET Value – – – – – – Read/Write Addressing Mode Register addressing only .7–.3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file.

  • Page 80: Sph Stack Pointer (High Byte)

    CONTROL REGISTERS S3C80M4/F80M4 — Stack Pointer (High Byte) Set 1 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8).
  • Page 81 S3C80M4/F80M4 CONTROL REGISTER STPCON — Stop Control Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, You must set this STPCON register as “10100101b”.
  • Page 82 CONTROL REGISTERS S3C80M4/F80M4 — System Mode Register Set 1 Bit Identifier RESET Value – – – – Read/Write Addressing Mode Register addressing mode only Not used, But you must keep "0" Not used for the S3C80M4 .6–.5 .4–.2 Fast Interrupt Level Selection Bits...
  • Page 83 S3C80M4/F80M4 CONTROL REGISTER T0CON — Timer 0 Control Register Set 1, Bank 0 Bit Identifier RESET Value Read/Write Addressing Mode Register addressing mode only .7–.5 Timer 0 Input Clock Selection Bits fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 External clock (T0CLK) falling edge...
  • Page 84 CONTROL REGISTERS S3C80M4/F80M4 NOTES 4-26...
  • Page 85 S3C80M4/F80M4 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware.
  • Page 86 INTERRUPT STRUCTURE S3C80M4/F80M4 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic.
  • Page 87 INTERRUPT STRUCTURE S3C80M4 INTERRUPT STRUCTURE The S3C80M4/F80M4 microcontroller supports nineteen interrupt sources. All nineteen of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device- specific interrupt structure, as shown in Figure 5-2.
  • Page 88 S3C80M4/F80M4 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C80M4/F80M4 interrupt structure are stored in the vector address area of the internal 4-Kbyte ROM, 0H–FFFH (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
  • Page 89 S3C80M4/F80M4 INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Interrupt Value Value Level √ 100H Basic timer overflow Reset √ Timer 0 match IRQ0 Reserved IRQ1 – – √ PWM interrupt IRQ2 Reserved IRQ3 –...
  • Page 90 Interrupt priority register Controls the relative processing priorities of the interrupt levels. The seven levels of S3C80M4/F80M4 are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
  • Page 91 S3C80M4/F80M4 INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) —...
  • Page 92 INTERRUPT STRUCTURE S3C80M4/F80M4 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers...
  • Page 93 S3C80M4/F80M4 INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is undetermined.
  • Page 94 INTERRUPT STRUCTURE S3C80M4/F80M4 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
  • Page 95 S3C80M4/F80M4 INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
  • Page 96 INTERRUPT STRUCTURE S3C80M4/F80M4 Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group priority: Group A: 0 = IRQ0 > IRQ1 D7 D4 D1 1 = IRQ1 > IRQ0 Group B: = Undefined 0 = IRQ2 > (IRQ3, IRQ4) = B >...
  • Page 97 S3C80M4/F80M4 INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 2 to IRQ2, and so on.
  • Page 98 INTERRUPT STRUCTURE S3C80M4/F80M4 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
  • Page 99 S3C80M4/F80M4 INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.
  • Page 100 INTERRUPT STRUCTURE S3C80M4/F80M4 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack.
  • Page 101 — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). NOTE For the S3C80M4/F80M4 microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1.
  • Page 102 INTERRUPT STRUCTURE S3C80M4/F80M4 NOTES 5-18...
  • Page 103 S3C80M4/F80M4 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...
  • Page 104 INSTRUCTION SET S3C80M4/F80M4 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load bit dst,src Load external data memory dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement...
  • Page 105 S3C80M4/F80M4 INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions dst,src Add with carry dst,src dst,src Compare Decimal adjust Decrement DECW Decrement word dst,src Divide Increment INCW Increment word MULT dst,src Multiply dst,src Subtract with carry...
  • Page 106 INSTRUCTION SET S3C80M4/F80M4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL Call procedure CPIJE dst,src Compare, increment and jump on equal...
  • Page 107 S3C80M4/F80M4 INSTRUCTION SET Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic SWAP Swap nibbles CPU Control Instructions Complement carry flag...
  • Page 108 INSTRUCTION SET S3C80M4/F80M4 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic.
  • Page 109 S3C80M4/F80M4 INSTRUCTION SET FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
  • Page 110 INSTRUCTION SET S3C80M4/F80M4 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
  • Page 111 S3C80M4/F80M4 INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Bit (b) of working register Rn.b (n = 0–15, b = 0–7) Bit 0 (LSB) of working register Rn (n = 0–15)
  • Page 112 INSTRUCTION SET S3C80M4/F80M4 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1.b, R2 BXOR r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r0–Rb SRP/0/1 BTJR IRR1 r1,r2 r1,Ir2 R2,R1...
  • Page 113 S3C80M4/F80M4 INSTRUCTION SET Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – DJNZ NEXT r1,R2 r2,R1 r1,RA cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ENTER EXIT IDLE ↓ ↓ ↓ ↓ ↓ ↓ ↓...
  • Page 114 INSTRUCTION SET S3C80M4/F80M4 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...
  • Page 115 S3C80M4/F80M4 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...

  • Page 116: Adc Add With Carry

    INSTRUCTION SET S3C80M4/F80M4 — Add with carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.

  • Page 117: Add Add

    S3C80M4/F80M4 INSTRUCTION SET — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.

  • Page 118: And Logical And

    INSTRUCTION SET S3C80M4/F80M4 — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...

  • Page 119: Band Bit And

    S3C80M4/F80M4 INSTRUCTION SET BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source).

  • Page 120: Bcp Bit Compare

    INSTRUCTION SET S3C80M4/F80M4 — Bit Compare dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison.

  • Page 121: Bitc Bit Complement

    S3C80M4/F80M4 INSTRUCTION SET BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.

  • Page 122: Bitr Bit Reset

    INSTRUCTION SET S3C80M4/F80M4 BITR — Bit Reset BITR dst.b dst(b) ← 0 Operation: The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode...

  • Page 123: Bits Bit Set

    S3C80M4/F80M4 INSTRUCTION SET BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. No flags are affected. Flags: Format: Bytes Cycles Opcode...
  • Page 124 INSTRUCTION SET S3C80M4/F80M4 — Bit OR dst,src.b dst.b,src dst(0) ← dst(0) OR src(b) Operation: dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination.

  • Page 125: Btjrf Bit Test, Jump Relative On False

    S3C80M4/F80M4 INSTRUCTION SET BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...

  • Page 126: Btjrt Bit Test, Jump Relative On True

    INSTRUCTION SET S3C80M4/F80M4 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b If src(b) is a "1", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...

  • Page 127: Bxor Bit Xor

    S3C80M4/F80M4 INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.

  • Page 128: Call Call Procedure

    INSTRUCTION SET S3C80M4/F80M4 CALL — Call Procedure CALL ← Operation: SP – 1 ← ← SP –1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.

  • Page 129: Ccf Complement Carry Flag

    S3C80M4/F80M4 INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

  • Page 130: Clr Clear

    INSTRUCTION SET S3C80M4/F80M4 — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: Examples: →...

  • Page 131: Com Complement

    S3C80M4/F80M4 INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. C: Unaffected. Flags: Z: Set if the result is "0"; cleared otherwise.

  • Page 132: Cp Compare

    INSTRUCTION SET S3C80M4/F80M4 — Compare dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise.

  • Page 133: Cpije Compare, Increment, And Jump On Equal

    S3C80M4/F80M4 INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.

  • Page 134: Cpijne Compare, Increment, And Jump On Non-Equal

    INSTRUCTION SET S3C80M4/F80M4 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA If dst – src "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement...

  • Page 135: Decimal Adjust

    S3C80M4/F80M4 INSTRUCTION SET — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not...
  • Page 136 INSTRUCTION SET S3C80M4/F80M4 — Decimal Adjust (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1,R0 R1 ←...

  • Page 137: Dec Decrement

    S3C80M4/F80M4 INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.

  • Page 138: Decw Decrement Word

    INSTRUCTION SET S3C80M4/F80M4 DECW — Decrement Word DECW dst ← dst – 1 Operation: The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one.

  • Page 139: Di Disable Interrupts

    S3C80M4/F80M4 INSTRUCTION SET — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

  • Page 140: Div Divide (Unsigned)

    INSTRUCTION SET S3C80M4/F80M4 — Divide (Unsigned) dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.

  • Page 141: Djnz Decrement And Jump If Non-Zero

    S3C80M4/F80M4 INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.

  • Page 142: Ei Enable Interrupts

    INSTRUCTION SET S3C80M4/F80M4 — Enable Interrupts SYM (0) ← 1 Operation: An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.
  • Page 143 S3C80M4/F80M4 INSTRUCTION SET ENTER — Enter ENTER ← Operation: SP – 2 ← ← ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.

  • Page 144: Exit Exit

    INSTRUCTION SET S3C80M4/F80M4 EXIT — Exit EXIT ← Operation: ← SP + 2 ← ← IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two.

  • Page 145: Idle Idle Operation

    S3C80M4/F80M4 INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.

  • Page 146: Inc Increment

    INSTRUCTION SET S3C80M4/F80M4 — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.

  • Page 147: Incw Increment Word

    S3C80M4/F80M4 INSTRUCTION SET INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

  • Page 148: Iret Interrupt Return

    INSTRUCTION SET S3C80M4/F80M4 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) FLAGS ← @SP PC ↔ IP Operation: SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine.

  • Page 149: Jp Jump

    S3C80M4/F80M4 INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.

  • Page 150: Jr Jump Relative

    INSTRUCTION SET S3C80M4/F80M4 — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...

  • Page 151: Ld Load

    S3C80M4/F80M4 INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) dst | opc...
  • Page 152 INSTRUCTION SET S3C80M4/F80M4 — Load (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...

  • Page 153: Ldb Load Bit

    S3C80M4/F80M4 INSTRUCTION SET — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.

  • Page 154: Ldc/Lde Load Memory

    INSTRUCTION SET S3C80M4/F80M4 LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
  • Page 155 S3C80M4/F80M4 INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: ;...

  • Page 156: Ldcd/Lded Load Memory And Decrement

    INSTRUCTION SET S3C80M4/F80M4 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.

  • Page 157: Ldci/Ldei Load Memory And Increment

    S3C80M4/F80M4 INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 158 INSTRUCTION SET S3C80M4/F80M4 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src rr ← rr – 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented.
  • Page 159 S3C80M4/F80M4 INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.

  • Page 160: Ldw Load Word

    INSTRUCTION SET S3C80M4/F80M4 — Load Word dst,src dst ← src Operation: The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...

  • Page 161: Mult Multiply (Unsigned)

    S3C80M4/F80M4 INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.
  • Page 162 INSTRUCTION SET S3C80M4/F80M4 NEXT — Next NEXT PC ← @ IP Operation: IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two.

  • Page 163: Nop No Operation

    S3C80M4/F80M4 INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected.

  • Page 164: Or Logical Or

    INSTRUCTION SET S3C80M4/F80M4 — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...

  • Page 165: Pop Pop From Stack

    S3C80M4/F80M4 INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. No flags affected.

  • Page 166: Popud Pop User Stack (Decrementing)

    INSTRUCTION SET S3C80M4/F80M4 POPUD — Pop User Stack (Decrementing) POPUD dst,src dst ← src Operation: IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented.

  • Page 167: Popui Pop User Stack (Incrementing)

    S3C80M4/F80M4 INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.

  • Page 168: Push Push To Stack

    INSTRUCTION SET S3C80M4/F80M4 PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.

  • Page 169: Pushud Push User Stack (Decrementing)

    S3C80M4/F80M4 INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.

  • Page 170: Pushui Push User Stack (Incrementing)

    INSTRUCTION SET S3C80M4/F80M4 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src IR ← IR + 1 Operation: dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer.

  • Page 171: Rcf Reset Carry Flag

    S3C80M4/F80M4 INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.

  • Page 172: Ret Return

    INSTRUCTION SET S3C80M4/F80M4 — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.

  • Page 173: Rl Rotate Left

    S3C80M4/F80M4 INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

  • Page 174: Rlc Rotate Left Through Carry

    INSTRUCTION SET S3C80M4/F80M4 — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...

  • Page 175: Rr Rotate Right

    S3C80M4/F80M4 INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

  • Page 176: Rrc Rotate Right Through Carry

    INSTRUCTION SET S3C80M4/F80M4 — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...

  • Page 177: Sb0 Select Bank 0

    S3C80M4/F80M4 INSTRUCTION SET — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file.

  • Page 178: Sb1 Select Bank 1

    INSTRUCTION SET S3C80M4/F80M4 — Select Bank 1 BANK ← 1 Operation: The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.)

  • Page 179: Sbc Subtract With Carry

    S3C80M4/F80M4 INSTRUCTION SET — Subtract with Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

  • Page 180: Scf Set Carry Flag

    INSTRUCTION SET S3C80M4/F80M4 — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. C: Set to "1". Flags: No other flags are affected. Format: Bytes Cycles Opcode (Hex)

  • Page 181: Sra Shift Right Arithmetic

    S3C80M4/F80M4 INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 182: Srp/Srp0/Srp1

    INSTRUCTION SET S3C80M4/F80M4 SRP/SRP0/SRP1 — Set Register Pointer SRP0 SRP1 ← If src (1) = 1 and src (0) = 0 then: RP0 (3–7) src (3–7) Operation: ← If src (1) = 0 and src (0) = 1 then: RP1 (3–7) src (3–7)

  • Page 183: Stop Stop Operation

    S3C80M4/F80M4 INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.

  • Page 184: Sub Subtract

    INSTRUCTION SET S3C80M4/F80M4 — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

  • Page 185: Swap Swap Nibbles

    S3C80M4/F80M4 INSTRUCTION SET SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.

  • Page 186: Tcm Test Complement Under Mask

    INSTRUCTION SET S3C80M4/F80M4 — Test Complement Under Mask dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

  • Page 187: Tm Test Under Mask

    S3C80M4/F80M4 INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.

  • Page 188: Wfi Wait For Interrupt

    INSTRUCTION SET S3C80M4/F80M4 — Wait for Interrupt Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt .
  • Page 189 S3C80M4/F80M4 INSTRUCTION SET — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
  • Page 190 INSTRUCTION SET S3C80M4/F80M4 NOTES 6-88...
  • Page 191 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C80M4/F80M4 by an external crystal can range from 0.4 MHz to 10 MHz. The maximum CPU clock frequency is 10 MHz. The X and X pins connect the external oscillator or clock source to the on-chip clock circuit.
  • Page 192 CLOCK CIRCUIT S3C80M4/F80M4 MAIN OSCILLATOR CIRCUITS Figure 7-1. Crystal/Ceramic Oscillator (fx) Figure 7-2. External Oscillator (fx) Figure 7-3. RC Oscillator (fx)
  • Page 193 S3C80M4/F80M4 CLOCK CIRCUIT CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock.
  • Page 194 CLOCK CIRCUIT S3C80M4/F80M4 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
  • Page 195 S3C80M4/F80M4 CLOCK CIRCUIT CLOCK OUTPUT CONTROL REGISTER (CLOCON) The clock output control register, CLOCON, is located in the bank 0 of set1, address E3H. It is read/write addressable and has the following functions; — Clock Output Frequency Selection After a reset, fxx/64 is select for Clock Output Frequency because the reset value of CLOCON.1-.0 is "0".
  • Page 196 CLOCK CIRCUIT S3C80M4/F80M4 STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in the bank 0 of set1, address FBH. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values".
  • Page 197 RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3C80M4/F80M4 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance.
  • Page 198 — An "x" means that the bit value is undefined after a reset. — A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1. S3C80M4/F80M4 Set 1 Register and Values After RESET Register Name...
  • Page 199 RESET S3C80M4/F80M4 and POWER-DOWN Table 8-2. S3C80M4/F80M4 Set 1, Bank 0 Register and Values After RESET Register Name Mnemonic Address Bit Values After RESET Port 0 Data Register Port 1 Data Register Location E2H is not mapped. Clock Output Control Register CLOCON –...
  • Page 200 External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The external interrupts in the S3C80M4/F80M4 interrupt structure that can be used to release Stop mode are: — External interrupts P0.0–P0.3 (INT0–INT3) Please note the following conditions for Stop mode release: —...
  • Page 201 RESET S3C80M4/F80M4 and POWER-DOWN IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active.
  • Page 202 RESET and POWER-DOWN S3C80M4/F80M4 NOTES...
  • Page 203 Alternately P1.0, P1.0, P1.6 can be used as T0OUT, T0CLK, CLKOUT. PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all four S3C80M4/F80M4 I/O port data registers. Data registers for ports 0 and 1 have the general format shown in Figure 9-1.
  • Page 204 I/O PORTS S3C80M4/F80M4 PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E0H in set 1, bank 0. P0.0–P0.7 can serve inputs, as output push pull or you can configure the following alternative functions: —...
  • Page 205 S3C80M4/F80M4 I/O PORTS Port 0 Control Register, High Byte (P0CONH) F2H, Set 1, Bank 0, R/W P0.7 P0.6 P0.5 P0.4 (PWM) P0CONH bit-pair pin configuration settings: Schmitt trigger input mode Schmitt trigger input mode, pull-up Alternative function (PWM,not used for P0.7/P0.5/P0.4) Output mode, push-pull Figure 9-1.
  • Page 206 I/O PORTS S3C80M4/F80M4 Port 0 Interrupt Control Register (P0INT) F4H, Set 1, Bank 0, R/W INT3 INT2 INT1 INT0 P0INT bit configuration settings: Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9-3.
  • Page 207 S3C80M4/F80M4 I/O PORTS PORT 1 Port 1 is an 7-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E1H in set 1, bank 0. P1.0–P1.6 can serve inputs, as outputs (push pull or open-drain) or you can configure the following alternative functions: —...
  • Page 208 I/O PORTS S3C80M4/F80M4 Port 1 Control Register, Low Byte (P1CONL) F0H, Set 1, Bank 0, R/W P1.0/T0OUT P1.1/T0CLK P1.2 P1.3 P1CONL bit-pair pin configuration settings: Input mode (T0CLK) Output mode, N-channel open-drain Alternative function ( T0OUT, not used for P1.3/P1.2/P1.1) Output mode, push-pull Figure 9-6.
  • Page 209 BASIC TIMER BASIC TIMER OVERVIEW S3C80M4/F80M4 has an 8-bit basic timer . BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or —...
  • Page 210 BASIC TIMER S3C80M4/F80M4 Basic TImer Control Register (BTCON) D3H, Set 1, R/W Divider clear bit: Watchdog timer enable bits: 0 = No effect 1010B = Disable watchdog function 1= Clear dvider Other value = Enable watchdog function Basic timer counter clear bit:...
  • Page 211 S3C80M4/F80M4 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function.
  • Page 212 BASIC TIMER S3C80M4/F80M4 RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus /4096 Clear /1024 8-Bit Up Counter /128 (BTCNT, Read-Only) RESET (NOTE) Start the CPU Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).
  • Page 213 S3C80M4/F80M4 8-BIT TIMER 0 8-BIT TIMER 0 OVERVIEW The 8-bit timer 0 is an 8-bit general-purpose timer/counter. Timer 0 has the following functional components: — Clock frequency divider (fxx divided by 1024, 256, 64, 8 or 1) with multiplexer — External clock input pin (T0CLK) —...
  • Page 214 8-BIT TIMER 0 S3C80M4/F80M4 TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Enable the timer 0 operating mode (interval timer) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT —...
  • Page 215 S3C80M4/F80M4 8-BIT TIMER 0 BLOCK DIAGRAM T0CON.7-.5 Data Bus /1024 /256 T0CON.3 Clear 8-bit Up-Counter (Read Only) T0CON.1 T0CLK Pending T0INT 8-bit Comparator T0CON.0 (IRQ0) Match Counter stop T0OUT Timer 0 Buffer Register T0CON.2 Counter clear signal (T0CON.3) or Match signal...
  • Page 216 8-BIT TIMER 0 S3C80M4/F80M4 NOTES 11-4...
  • Page 217 S3C80M4/F80M4 8-BIT PULSE WIDTH MODULATION 8-BIT PULSE WIDTH MODULATION OVERVIEW The S3C80M4/F80M4 microcontroller has a 8-bit PWM. The PWM have the following components: — Clock frequency dividers (f divider by 64, 8, 2 and 1) — 6-bit counter, 6-bit comparators and data registers (PWMDATA) —...
  • Page 218 8-BIT PULSE WIDTH MODULATION S3C80M4/F80M4 8-BIT PULSE WIDTH MODULATION (PWMCON) The PWM control register, PWMCON is used to select the PWM interrupt to enable or disable the PWM function. It is located in set 1, bank 0 at address E8H, and is read/write addressable using register addressing mode.
  • Page 219 S3C80M4/F80M4 8-BIT PULSE WIDTH MODULATION BLOCK DIAGRAM PWMCON.7-.6 PWM/P0.6 fosc/64 From 8-Bit Up Counter(5:0) From 8-Bit Up Counter(7:6) fosc/8 6-Bit Counter 2-Bit Counter fosc/2 fosc/1 "1" When Extension REG > Count Control Logic 6-Bit Comparator PWMCON.2 "1" When REG = Count...
  • Page 220 8-BIT PULSE WIDTH MODULATION S3C80M4/F80M4 NOTES 12-4...
  • Page 221 S3C80M4/F80M4 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C80M4/F80M4 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Input/output capacitance — A.C. electrical characteristics —...
  • Page 222 ELECTRICAL DATA S3C80M4/F80M4 Table13-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply voltage – – 0.3 to +6.5 – 0.3 to V + 0.3 Input voltage Ports 0-1 – 0.3 to V + 0.3 Output voltage –...
  • Page 223 S3C80M4/F80M4 ELECTRICAL DATA Table 13-2. D.C. Electrical Characteristics (Continued) ° ° = –25 C to + 85 C, V = 2.4V to 5.5V) Parameter Symbol Conditions Unit Output high = 4.5V to 5.5V –1.0 – – voltage = –1 mA All output pins = 4.5V to 5.5V...
  • Page 224 ELECTRICAL DATA S3C80M4/F80M4 Table 13-2. D.C. Electrical Characteristics (Continued) ° ° = –25 C to + 85 C, V = 2.4 V to 5.5 V) Parameter Symbol Conditions Unit Supply current Run mode: 10 MHz – Crystal oscillator C1 = C2 = 22pF 4.0 MHz...
  • Page 225 S3C80M4/F80M4 ELECTRICAL DATA Table 13-3. A.C. Electrical Characteristics ° ° = –25 C to +85 C, V = 2.4 V to 5.5 V) Parameter Symbol Conditions Unit Interrupt input All interrupt, V = 3.0 V – INTH INTL high, low width µs...
  • Page 226 ELECTRICAL DATA S3C80M4/F80M4 Table 13-4. Input/Output Capacitance ° ° = –25 C to +85 C, V = 2.4 V to 5.5 V) Parameter Symbol Conditions Unit Input f = 1 MHz; unmeasured pins – – are returned to V capacitance...
  • Page 227 S3C80M4/F80M4 ELECTRICAL DATA Idle Mode (Basic Timer Active) Stop Mode Normal Data Retention Mode Operating Mode DDDR Execution of 0.8V STOP Instruction WAIT NOTE: is the same as 16 x 1/BT clock. WAIT Figure 13-4. Stop Mode Release Timing Initiated by Interrupt...
  • Page 228 ELECTRICAL DATA S3C80M4/F80M4 Table13-6. Main Oscillator Characteristics ° ° (T A = –25 C to +85 C, V = 2.4V to 5.5V) Oscillator Clock Configuration Parameter Test Condition Units Crystal Main oscillation 2.7 V – 5.5 V – frequency 2.4 V – 5.5 V –...
  • Page 229 S3C80M4/F80M4 ELECTRICAL DATA Table 13-7. Main Oscillation Stabilization Time = –25 ° C to + 85 ° C, V = 2.4V to 5.5V) Oscillator Test Condition Unit Crystal fx > 1 MHz – – Oscillation stabilization occurs when V Ceramic –...
  • Page 230 ELECTRICAL DATA S3C80M4/F80M4 NOTES 13-10...
  • Page 231 S3C80M4/F80M4 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C80M/F80M4 microcontroller is currently available in 20-DIP-300A/20-SOP-375 and 16-DIP-300A/16- SOP-375 package. 0-15 20-DIP-300A 26.80 MAX ± 0.20 26.40 ± 0.10 0.46 2.54 ± 0.10 (1.77) 1.52 NOTE: Dimensions are in millimeters. Figure 14-1. 20-DIP-300A Package Dimensions...
  • Page 232 MECHANICAL DATA S3C80M4/F80M4 20-SOP-375 + 0.10 0.203 - 0.05 13.14 MAX ± 0.20 12.74 0.10 MAX 1.27 (0.66) + 0.10 0.40 - 0.05 NOTE: Dimensions are in millimeters. Figure 14-2. 20-SOP-375 Package Dimensions 14-2...
  • Page 233 S3C80M4/F80M4 MECHANICAL DATA 0-15 16-DIP-300A 19.80 MAX 19.40 ± 0.20 0.46 2.54 (0.81) 1.50 NOTE: Dimensions are in millimeters. Figure 14-3. 16-DIP-300A Package Dimensions 14-3...
  • Page 234 MECHANICAL DATA S3C80M4/F80M4 16-SOP-375 + 0.10 0.203 - 0.05 10.50 MAX ± 0.20 10.10 0.10 MAX 1.27 (0.66) + 0.10 0.40 - 0.05 NOTE: Dimensions are in millimeters. Figure 14-4. 16-SOP-375 Package Dimensions 14-4...
  • Page 235 S3C80M4/F80M4 S3F80M4 FLASH MCU S3F80M4 FLASH MCU OVERVIEW The S3F80M4 single-chip CMOS microcontroller is the Flash MCU version of the S3C80M4 microcontroller. It has an on-chip Flash MCU ROM instead of a masked ROM. The Flash ROM is accessed by serial data format.
  • Page 236 S3F80M4 FLASH MCU S3C80M4/F80M4 P0.0/INT0/SCLK P0.1/INT1/SDAT P0.2/INT2 S3F80M4 /nRESET (20-DIP-300A) P0.3/INT3 P1.0/T0OUT (20-SOP-375) P0.4 P1.1/T0CLK P0.5 P1.2 P0.6/PWM P1.3 P0.7 P1.4 P1.5 P1.6/CLKOUT Figure 15-1. S3F80M4 Pin Assignments (20-DIP-300A, 20-SOP-375) 15-2...
  • Page 237 S3C80M4/F80M4 S3F80M4 FLASH MCU P0.0/INT0/SCLK P0.1/INT1/SDAT /nRESET P0.2/INT2 S3F80M4 (16-DIP-300A) P1.0/T0OUT P0.3/INT3 (16-SOP-375) P1.1/T0CLK P0.4 P1.2 P0.5 P1.3 P0.6/PWM Figure 15-2. S3F80M4 Pin Assignments (16-DIP-300A, 16-SOP-375) 15-3...
  • Page 238 S3F80M4 FLASH MCU S3C80M4/F80M4 Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. Function P0.1 SDAT 18(14) Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port.
  • Page 239 S3C80M4/F80M4 S3F80M4 FLASH MCU OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V (nRESET) pin of the S3C80M4, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below.
  • Page 240 S3F80M4 FLASH MCU S3C80M4/F80M4 Instruction Clock fx (Main oscillation frequency) 10 MHz 2.5 MHz 4.2 MHz 1.05 MHz 6.25 kHz(Main) 400 kHz(Main) Supply Voltage (V) Minimum instruction clock = 1/4n x oscillator frequency (n = 1,2,8,16) Figure 15-3. Operating Voltage Range...
  • Page 241 SMDS2+, and OPENice for S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.
  • Page 242 DEVELOPMENT TOOLS S3C80M4/F80M4 IBM-PC AT or Compatible RS-232C SMDS2+ Target PROM/OTP Writer Unit Application System RAM Break/Display Unit Probe Adapter Trace/Timer Unit TB80M4 Target SAM8 Base Unit Board Power Supply Unit Chip Figure 16-1. SMDS Product Configuration (SMDS2+) 16-2...
  • Page 243 S3C80M4/F80M4 DEVELOPMENT TOOLS TB80M4 TARGET BOARD The TB80M4 target board is used for the S3C80M4/F80M4 microcontroller. It is supported with the SMDS2+. TB80M4 To User_V Idle Stop 7411 RESET Smart Option Selection XTAL High Smart Option Source Device Selection J102...
  • Page 244 DEVELOPMENT TOOLS S3C80M4/F80M4 Table 16-1. Power Selection Settings for TB80M4 "To User_Vcc" Operating Mode Comments Settings The SMDS2/SMDS2+ To User_V supplies V to the target TB80M4 Target board (evaluation chip) and System the target system. SMDS2/SMDS2+ The SMDS2/SMDS2+ To User_V...
  • Page 245 S3C80M4/F80M4 DEVELOPMENT TOOLS Table 16-3. Device Selection Settings for TB80M4 "Device Selection" Operating Mode Comments Settings Operate with TB84G5 Device Selection Target 80M4 84G5 TB84G5 System Operate with TB80M4 Device Selection Target 80M4 84G5 TB80M4 System SMDS2+ SELECTION (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows.
  • Page 246 DEVELOPMENT TOOLS S3C80M4/F80M4 Table 16-5. Smart Option Source Settings for TB80M4 "Smart Option Source" Operating Mode Comments Settings Always must keep the External. Select Smart Option Source Target TB80M4 Internal External System Do not setting on left figure. Select Smart...
  • Page 247 S3C80M4/F80M4 DEVELOPMENT TOOLS J101 P0.0/INT0 P0.1/INT1 nRESET P0.2/INT2 P0.3/INT3 P1.0/T0OUT P1.1/T0CLK P0.4 P1.2 P0.5 P1.3 P0.6PWM P1.4 P0.7 P1.6/CLKOUT P1.5 S3C80M4 20-DIP Figure 16-3. 20-Pin Connectors (J101) for TB80M4 Target Board Target System J101 J101 (1) (16) (1) (16) Target Cable for 16/20-Pin Connector...
  • Page 248 DEVELOPMENT TOOLS S3C80M4/F80M4 NOTES 16-8...
  • Page 249 This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.

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