Samsung S3P80C5 User Manual page 228

S3P80C5/C80C5/C80C8
1/4096
1/1024
DIV
X
IN
1/128
R
Bit 0
1/4096
R
1/1024
DIV
1/128
P2.1/T0CK
NOTES:
1. During a power-on reset operation, the CPU is idle during the required oscillation
stabilizatiin interval (until bit 4 of the basic timer counter overflows).
2. It is available only in using interval mode.
Bit 1
RESET
or Stop
Bits 3,2
Clear
8-Bit Basic Counter
MUX
(Read-Only)
Bits 7,6
Data Bus
8-Bit Up-Counter
MUX
(Read-Only)
8-Bit Comparator
Timer 0 Buffer Reg
Timer 0 Data Register
(Read/Write)
Data Bus
Figure 10-5. Basic Timer and Timer 0 Block Diagram
Basic Timer Control Register
(Write '1010xxxxB' to disable)
Data Bus
OVF
OVF
Bit 3
Clear
R
(2)
Match
Bits 5,4
Match Signal
T0CON.3
T0OVF
Basic Timer Control Register
Timer 0 Control Register
BASIC TIMER AND TIMER 0
RESET
Bit 2
T0CON.0
Bit 1 PND
T0PWM
P2.0
T0INT
10-7