Samsung S3P80C5 User Manual page 202

S3P80C5/C80C5/C80C8
8
RESET and POWER-DOWN RESET
SYSTEM RESET
S3P80C5/C80C5/C80C8 has four different system reset sources as followings:
— Low Voltage Detect (LVD)
— Internal POR circuit
— INTR (Interrupt with RESET)
— Basic Timer (Watchdog timer)
LVD RESET
The Low Voltage detect circuit is built on the S3P80C5/C80C5/C80C8 product for system reset not in stop mode.
When the operating status is not stop mode it detects a slope of V
(Low level Detect Voltage). The reset pulse is generated by the rising slope of V
rising up and passing V
when the operating state is "stop mode" to reduce the current consumption under 1 uA instead of 6 uA.
LVD
Stop
STOPCON
INTR
POR
BT(WDT)
Figure 8-1. Reset Block Diagram
, the reset pulse is occurred at the moment "V
LVD
Enable/Disable
Noise
Filter
DD
RESET RESET
by comparing the voltage at V
. While the voltage at V
DD
>= V
". This function is disabled
DD LVD
and POWER-DOWN
with V
DD LVD
is
DD
8-1