Samsung S3P80C5 User Manual page 203

RESET RESET
and POWER-DOWN
INTERRUPT WITH RESET(INTR)
A non vectored interrupt called Interrupt with reset (INTR) is built in
S3C80C5/C80C8 to release stop status with system reset. When a falling/rising edge occurs at Port 0 during stop
mode, INTR signal is generated and it makes the system reset pulse. An INTR signal is generated relating to
interaction between Port 0 and operating status. It is enabled by STOP status and occurs by falling/rising edge at
port0. So only when the chip status is "STOP", it is available. If the operating status is not stop status INTR does
not occurs.
This INTR is supplementary function to make system reset for an application which is using " stop mode"
like remote controller. If an application which is not using "stop mode" , INTR function can be discarded.
WATCHDOG TIMER RESET
The S3P80C5/C80C5/C80C8 build a watch-dog timer that can recover to normal operation from abnormal
function. Watchdog timer generates a system reset signal if not clearing a BT-Basic Counter within a specific
time by program. System reset can return to the proper operation of chip.
POWER-ON RESET(POR)
The power-on reset circuit is built on the S3P80C5/C80C5/C80C8 product. During a power-on reset, the voltage
at V goes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High
DD
level. The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the
Schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal
capacitor, and a Schmitt trigger input transistor.
8-2
NOTE
V
DD
R : On-Chip Resistor
C : On-Chip Capacitor
C
Schmitt Trigger Inverter
V
SS
Figure 8-2. Power-on Reset Circuit
S3P80C5/C80C5/C80C8
System Reset