Samsung S3P80C5 User Manual page 100

S3P80C5/C80C5/C80C8
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by that peripheral (see Table 5-3).
Interrupt Source
Timer 0 match or timer 0
overflow
Timer 1 match or timer 1
overflow
Counter A
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
NOTE: Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers
control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending
bits for the timer 0 and timer 1 match interrupts, respectively.
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Level
IRQ0
IRQ1
IRQ4
IRQ7
IRQ6
Register(s)
(note)
T0CON
T0DATA
(note)
T1CON
T1DATAH, T1DATAL
CACON
CADATAH, CADATAL
P0CONH
P0INT
P0PND
P0CONL
P0INT
P0PND
INTERRUPT STRUCTURE
Location(s) in Set 1
D2H
D1H
FAH
F8H, F9H
F3H
F4H, F5H
E8H
F1H
F2H
E9H
F1H
F2H
5-9