Samsung S3P80C5 User Manual page 70

S3P80C5/C80C5/C80C8
CLKCON
— System Clock Control Register
Bit Identifier
RESET Value RESET
Read/Write
Addressing Mode
.7–.6
.6–.5
.4–.3
.2–.0
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits are required only for systems that have a main clock and a subsystem clock. The
S3P80C5/C80C5/C80C8 uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
.7 .6
0 0
R/W R/W
Register addressing mode only
Oscillator IRQ Wake-up Function Enable Bit
Not used for S3P80C5/C80C5/C80C8.
Main Oscillator Stop Control Bits
Not used for S3P80C5/C80C5/C80C8.
CPU Clock (System Clock) Selection Bits
f /16
0 0
OSC
f /8
0 1
OSC
f /2
1 0
OSC
f (non-divided)
1 1
OSC
Subsystem Clock Selection Bit
1 0 1 Invalid setting for S3P80C5/C80C5/C80C8.
Other value Select main system clock (MCLK)
.5 .4
0 0
R/W R/W R/W
(1)
(2)
CONTROL REGISTERS
D4H
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W
4-7