Samsung KS86C6004 Manual
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Samsung KS86C6004 Manual

Samsung KS86C6004 Manual

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Product Overview
Address Spaces
Addressing Modes
Control Registers
Interrupt Structure
SAM87RI Instruction Set

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Summary of Contents for Samsung KS86C6004

  • Page 1 Product Overview Address Spaces Addressing Modes Control Registers Interrupt Structure SAM87RI Instruction Set...

  • Page 2: Product Overview

    Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The KS86C6004 has 4 K bytes of program memory on-chip and KS86C6008 has 8 K bytes.
  • Page 3 PRODUCT OVERVIEW KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) FEATURES Timer/Counter • SAM87RI CPU core • One 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function Memory • One 8-bit timer/counter with Compare/Overflow • 8-Kbyte internal program memory (ROM) •...

  • Page 4: Block Diagram

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PRODUCT OVERVIEW BLOCK DIAGRAM P1.0 P0.0 0.7/INT2 P2.0 2.7 / INT0 PORT 0 PORT 1 PORT 2 SAM87RI BUS P3.0 P3.1 I/O PORT AND PORT 3 P3.2 INTERRUPT CONTROL P3.3/CLO P4.0 / INT1 P4.1 / INT1...

  • Page 5: Pin Assignments

    PRODUCT OVERVIEW KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PIN ASSIGNMENTS P3.1 P3.2 P3.0 P3.3/CLO INT0 / P2.0 INT0 / P2.1 INT0 / P2.2 3.3 V INT0 / P2.3 VSS2 INT0 / P2.4 P0.0 / INT2 INT0 / P2.5 P0.1 / INT2 INT0 / P2.6 P0.2 / INT2...
  • Page 6 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PRODUCT OVERVIEW P1.0 3.3 V P1.1 P1.2 P1.3 P3.3/CLO P1.4 KS86C6004 P3.2 P1.5 P3.1 KS86C6008 P1.6 P3.0 (Top View) P1.7 P2.0/INT0 P4.3/INT1 P2.1/INT0 P4.2/INT1 P2.2/INT0 P2.3/INT0 RESET Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

  • Page 7: Pin Descriptions

    PRODUCT OVERVIEW KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PIN DESCRIPTIONS Table 1-1. KS86C6004/C6008/P6008 Pin Descriptions Circuit Share Names Type Description Number Numbers Pins Bit-programmable I/O port for Schmitt trigger P0.0-P0.7 36–29 INT2 input or open-drain output. Port0 can be (30–23) individually configured as external interrupt inputs.

  • Page 8: Pin Circuits

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PRODUCT OVERVIEW PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the KS86C6004/C6008/P6008 Circuit Number Circuit Type KS86C6004/C6008/P6008 Assignments RESET signal input Ports 0, 1, and 2 Port 3 Port 4 PULL-UP RESISTOR PULL-UP ENABLE OUTPUT PULL-UP...
  • Page 9 PRODUCT OVERVIEW KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) OUTPUT DATA OPEN DRAIN OUTPUT DISABLE INPUT DATA MODE INPUT DATA OUTPUT INPUT Figure 1-6. Pin Circuit Type C (Port 3)
  • Page 10 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PRODUCT OVERVIEW PULL-UP RESISTOR PULL-UP ENABLE OUTPUT DATA OPEN DRAIN OUTPUT DISABLE INPUT DATA MODE INPUT DATA OUTPUT INPUT Figure 1-7. Pin Circuit Type D (Port 4)

  • Page 11: Application Circuit

    PRODUCT OVERVIEW KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) APPLICATION CIRCUIT TEST KS86C6004 KS86C6008 RESET KEYBOARD MATRIX Figure 1-8. Keyboard Application Circuit Diagram 1-10...

  • Page 12: Address Spaces

    A 13-bit address bus supports both program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The KS86C6004 has 4 K bytes of mask-programmable program memory on-chip and KS86C6008 has 8 K bytes. There is one program memory configuration option: —...

  • Page 13: Program Memory (Rom)

    PROGRAM MEMORY (ROM) Normal Operating Mode (Internal ROM) The KS86C6004 has 4 K bytes (locations 0H–0FFFH) of internal mask-programmable program memory. The KS86C6008/P6008 has 8 K bytes (locations 0H–1FFFH) of internal mask-programmable program memory. The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address.

  • Page 14: Register Architecture

    ADDRESS SPACES REGISTER ARCHITECTURE The upper 64 bytes of the KS86C6004/C6008/P6008's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192 bytes of internal register file (00H–BFH) is called the general purpose register space . The total addressable register space is thereby 256 bytes. 233 registers in this space can be accessed.;...
  • Page 15 ADDRESS SPACES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PERIPHERAL CONTROL REGISTERS 64 BYTES OF COMMON AREA SYSTEM CONTROL REGISTERS WORKING REGISTERS GENERAL PURPOSE REGISTER FILE BYTES and STACK AREA Figure 2-2. Internal Register File Organization...

  • Page 16: Common Working Register Area (C0H-Cfh)

    However, because the KS86C6004/C6008/P6008 uses only page 0, you can use the common area for any internal data operation. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register.

  • Page 17: System Stack

    Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the KS86C6004/C6008/P6008, the SP must be initialized to an 8-bit value in the range 00H–BFH.
  • Page 18 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESS SPACES PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: ; SP ← C0H (Normally, the SP is set to 0C0H by the SP,#0C0H ;...
  • Page 19 ADDRESS SPACES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) NOTES...
  • Page 20 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 21: Register Addressing Mode (R)

    ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2).

  • Page 22: Indirect Register Addressing Mode (Ir)

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
  • Page 23 ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INDIRECT REGISTER ADDRESSING MODE (Continued) REGISTER FILE PROGRAM MEMORY REGISTER EXAMPLE PAIR INSTRUCTION POINTS TO OPCODE REFERENCES REGISTER PAIR PROGRAM 16-BIT MEMORY ADDRESS POINTS TO PROGRAM PROGRAM MEMORY MEMORY SAMPLE INSTRUCTIONS: VALUE USED IN...
  • Page 24 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) REGISTER FILE PROGRAM MEMORY 4-BIT 4 LSBs WORKING OPERAND REGISTER POINTS TO THE ADDRESS OPCODE WORKING REGISTER (1 OF 16) SAMPLE INSTRUCTION: VALUE USED IN OPERAND R6,@R2 INSTRUCTION Figure 3-5. Indirect Working Register Addressing to Register File...
  • Page 25 ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INDIRECT REGISTER ADDRESSING MODE (Concluded) REGISTER FILE PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS NEXT 3 BITS REGISTER OPCODE PAIR POINT TO EXAMPLE WORKING INSTRUCTION REGISTER PAIR 16-BIT REFERENCES (1 OF 8) ADDRESS EITHER POINTS TO...

  • Page 26: Indexed Addressing Mode (X)

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.
  • Page 27 ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INDEXED ADDRESSING MODE (Continued) REGISTER FILE PROGRAM MEMORY 4-BIT XS(OFFSET) REGISTER NEXT 3 BITS WORKING PAIR REGISTER 16-BIT POINT TO ADDRESS OPCODE ADDRESS WORKING ADDED TO REGISTER PAIR OFFSET (1 OF 8) LSB SELECTS...
  • Page 28 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) REGISTER FILE PROGRAM MEMORY (OFFSET) 4-BIT (OFFSET) REGISTER NEXT 3 BITS WORKING PAIR REGISTER 16-BIT POINT TO ADDRESS OPCODE ADDRESS WORKING ADDED TO REGISTER PAIR OFFSET (1 OF 8) LSB SELECTS...

  • Page 29: Direct Address Mode (Da)

    ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
  • Page 30 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ADDRESSING MODES DIRECT ADDRESS MODE (Continued) PROGRAM MEMORY NEXT OPCODE PROGRAM MEMORY ADDRESS USED LOWER ADDR BYTE UPPER ADDR BYTE OPCODE SAMPLE INSTRUCTIONS: C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Figure 3-11.

  • Page 31: Relative Address Mode (Ra)

    ADDRESSING MODES KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 32: Control Registers

    CONTROL REGISTERS CONTROL REGISTERS In this section, detailed descriptions of the KS86C6004/C6008/P6008 control registers are presented in an easy- to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.
  • Page 33 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 4-1. System and Peripheral control Registers Register Name Mnemonic Decimal Timer 0 counter register T0CNT Timer 0 data register T0DATA Timer 0 control register T0CON Location D3H is not mapped. Clock control register...
  • Page 34 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS Table 4-1. System and Peripheral control Registers (Continued) Register Name Mnemonic Decimal USB function address register FADDR Control endpoint status register EP0CSR Interrupt endpoint status register EP1CSR Control endpoint byte count register EP0BCNT Control endpoint FIFO register...
  • Page 35 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Bit number(s) that is/are appended to Name of individual the register name for bit addressing bit or bit function Register Register address mnemonic (hexadecimal) Full register name FLAGS System Flags Register Bit Identifier RESET...
  • Page 36 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS BTCON — Basic Timer Control Register Bit Identifier RESET Value Read/Write .7–.4 Watchdog Timer Enable Bits Disable watchdog function Any other value Enable watchdog function .3 and .2 Basic Timer Input Clock Selection Bits...

  • Page 37: System Clock Control Register

    CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CLKCON — System Clock Control Register Bit Identifier RESET Value Read/Write Oscillator IRQ Wake-up Function Bit Enable IRQ for main system oscillator wake-up in power down mode Disable IRQ for main system oscillator wake-up in power down mode Not used for KS86C6004/C6008/P6008 .6 and .5...
  • Page 38 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS EP0CSR — Control Endpoint 0 Status Register Bit Identifier RESET Value Read/Write Setup Data End Clear Bit No effect (when write) To clear SETUP_END bit Out Packet Ready Clear Bit No effect (when write)
  • Page 39 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) EP1CSR — Control Endpoint 1 Status Register Bit Identifier RESET Value Read/Write Data Toggle Sequence Clear Bit No effect (when write) MCU sets this bit to clear the data toggle sequence bit. The data toggle is initialized to DATA0.
  • Page 40 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS FADDR — USB Function Address Register Bit Identifier RESET Value Read/Write Not used for KS86C6004/C6008/P6008 .6–.0 FADDR This register holds the USB address assigned by the host computer. FADDR is located at address F0H and is read/write addressable.
  • Page 41 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) FLAGS — System Flags Register Bit Identifier – – – – RESET Value Read/Write Carry Flag (C) Operation does not generate a carry or borrow condition Zero Flag (Z) Operation result is a non-zero value...
  • Page 42 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P0CONH — Port 0 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 0, P0.7 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up...
  • Page 43 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P0CONL — Port 0 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 0, P0.3 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up...
  • Page 44 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P0INT — Port 0 Interrupt Control Register Bit Identifier RESET Value Read/Write P0.7 Configuration Bits External interrupt disable External interrupt enable P0.6 Configuration Bits External interrupt disable External interrupt enable P0.5 Configuration Bits External interrupt disable External interrupt enable P0.4 Configuration Bits...
  • Page 45 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P0PND — Port 0 Interrupt Pending Register Bit Identifier RESET Value (NOTE) Read/Write P0.7 Interrupt Pending Bit No pending (when read)/clear pending bit (when write) Pending (when read)/no effect (when write) P0.6 Interrupt Pending Bit...
  • Page 46 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P1CONH — Port 1 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 1, P1.7 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up .5 and .4...
  • Page 47 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P1CONL — Port 1 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 1, P1.3 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up .5 and .4...
  • Page 48 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P2CONH — Port 2 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 2, P2.7 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up...
  • Page 49 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P2CONL — Port 2 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7 and .6 Port 2, P2.3 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up...
  • Page 50 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P2INT — Port 2 Interrupt Enable Register Bit Identifier RESET Value Read/Write P2.7 Interrupt Enable Bit External interrupt disable External interrupt enable P2.6 Interrupt Enable Bit External interrupt disable External interrupt enable P2.5 Interrupt Enable Bit...
  • Page 51 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P2PND — Port 2 Interrupt Pending Register Bit Identifier RESET Value (NOTE) Read/Write P2.7 Interrupt Pending Bit No pending (when read)/clear pending bit (when write) Pending (when read)/no effect (when write) P2.6 Interrupt Pending Bit...
  • Page 52 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P3CON — Port 3 Control Register Bit Identifier RESET Value Read/Write .7 and .6 Port 3, P3.3 Configuration Bits Schmitt trigger input System clock output(CLO) mode. CLO comes from system clock circuit. Push-pull output N-channel open-drain output mode .5 and .4...
  • Page 53 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P4CON — Port 4 Control Register Bit Identifier RESET Value Read/Write .7 and .6 Port 4, P4.3 Configuration Control Bits Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode with pull-up...
  • Page 54 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS P4INTPND — Port 4 Interrupt Enable and Pending Register Bit Identifier RESET Value Read/Write P4.3 Interrupt Enable Bit External interrupt disable External interrupt enable P4.2 Interrupt Enable Bit External interrupt disable External interrupt enable P4.1 Interrupt Enable Bit...
  • Page 55 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PWRMGR — USB Power Management Register Bit Identifier RESET Value Read/Write Not used for KS86C6004/C6008/P6008 .7–.2 RESUME Signal Sending Bit RESUME signal is ended While in suspend state, if the MCU wants to initiate a resume, it writes a 1 to this register for 10ms (maximum of 15ms), and clears this register.
  • Page 56 Disable global interrupt processing Enable global interrupt processing .1 and .0 Page Selection Bits Addressing page 0 locations for KS86C6004/C6008/P6008 Other values Enable global interrupt processing NOTE: SYM must be selected bit 1 and 0 into 00 for KS86C6004/C6008/P6008. 4-25...
  • Page 57 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) T0CON — Timer 0 Control Register Bit Identifier RESET Value Read/Write .7 and .6 T0 Counter Input Clock Selection Bits CPU clock/4096 CPU clock/256 CPU clock/8 Invalid selection .5 and .4 T0 Operating Mode Selection Bits...
  • Page 58 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS USBPND — USB Interrupt Pending Register Bit Identifier RESET Value Read/Write Not used for KS86C6004/C6008/P6008 .7–.4 RESUME Interrupt Pending Bit No effect (once read, this bit is cleared automatically) While in suspend mode, if resume signaling is received this bit gets set...
  • Page 59 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) USBINT — USB Interrupt Enable Register Bit Identifier RESET Value Read/Write Not used for KS86C6004/C6008/P6008 .7–.3 SUSPEND/RESUME Interrupt Enable Bit Disable SUSPEND and RESEME interrupt Enable SUSPEND and RESEME interrupt ENDPOINT1 Interrupt Pending Bit...
  • Page 60 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL REGISTERS USBRST — USB RESET Register Bit Identifier – – – – – – – RESET Value Read/Write Not used for KS86C6004/C6008/P6008 .7–.1 USB Reset Signal Receive Bit No effect (this is automatically cleared once read)
  • Page 61 CONTROL REGISTERS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) NOTES 4-30...

  • Page 62: Interrupt Structure

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM87RI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H.

  • Page 63: Interrupt Pending Function Types

    INTERRUPT STRUCTURE KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RI, the order of service is determined by a sequence of source which is executed in interrupt service routine.

  • Page 64: Interrupt Source Service Sequence

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal.
  • Page 65 INTERRUPT STRUCTURE KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) KS86C6004/C6008/P6008 INTERRUPT STRUCTURE The KS86C6004/C6008/P6008 microcontroller has fourteen peripheral interrupt sources: — Timer 0 match interrupt — Timer 0 overflow interrupt — Eight external interrupts for port 2, P2.0–P2.7 — Four external interrupts for port 4, P4.0–P4.3...

  • Page 66: Register Addressing

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET SAM87RI Instruction Set OVERVIEW The SAM87RI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
  • Page 67 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions Clear dst,src Load dst,src Load program memory LDCD dst,src Load program memory and decrement LDED dst,src Load external data memory and decrement LDCI...
  • Page 68 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL Call procedure IRET Interrupt return cc,dst Jump on condition code Jump unconditional cc,dst Jump relative on condition code Return Bit Manipulation Instructions...

  • Page 69: Flags Register (Flags)

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

  • Page 70: Instruction Set Notation

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation –...
  • Page 71 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6-6. Working register only Rn (n = 0–15) Working register pair RRp (p = 0, 2, 4, ..., 14) Register or working register reg or Rn (reg = 0–255, n = 0–15)
  • Page 72 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) — r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM r1,r2...
  • Page 73 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) — r1,R2 r2,R1 cc,RA r1,IM cc,DA ↓ ↓ ↓ ↓ ↓ ↓ IDLE ↓ ↓ ↓ ↓ ↓ ↓ STOP IRET ↓...

  • Page 74: Condition Codes

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"...

  • Page 75: Instruction Descriptions

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM87RI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...

  • Page 76: Adc - Add With Carry

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Add With Carry dst,src dst ← dst + src + c Operation: The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed.
  • Page 77 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.
  • Page 78 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Logical AND dst,src dst ← dst AND src Operation: The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones;...

  • Page 79: Call Procedure

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CALL — Call Procedure CALL ← Operation: SP–1 ← ← SP–1 ← ← The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.

  • Page 80: Ccf - Complement Carry Flag

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.
  • Page 81 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Clear dst ← "0" Operation: The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode (Hex) Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: Examples: →...
  • Page 82 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.
  • Page 83 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Compare dst,src dst – src Operation: The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison.

  • Page 84: Dec - Decrement

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise.

  • Page 85: Di - Disable Interrupts

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Disable Interrupts SYM (2) ← 0 Operation: Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

  • Page 86: Ei - Enable Interrupts

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Enable Interrupts SYM (2) ← 1 Operation: An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.

  • Page 87: Idle - Idle Operation

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation.

  • Page 88: Inc - Increment

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Increment dst ← dst + 1 Operation: The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise.

  • Page 89: Iret - Interrupt Return

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) IRET — Interrupt Return IRET IRET FLAGS ← @SP Operation: SP ← SP + 1 PC ← @SP SP ← SP + 2 SYM(2) ← 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter.
  • Page 90 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.

  • Page 91: Jr - Jump Relative

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Jump Relative cc,dst If cc is true, PC ← PC + dst Operation: If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter;...
  • Page 92 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode Addr Mode...
  • Page 93 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Load (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, Examples: register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: → R0,#10H R0 = 10H →...

  • Page 94: Load Memory

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src dst ← src Operation: This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory.
  • Page 95 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) LDC/LDE — Load Memory LDC/LDE (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program Examples: memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.

  • Page 96: Load Memory And Decrement

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src dst ← src Operation: rr ← rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.

  • Page 97: Load Memory And Increment

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file.

  • Page 98: Nop - No Operation

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.
  • Page 99 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Logical OR dst,src dst ← dst OR src Operation: The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1";...

  • Page 100: Pop - Pop From Stack

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.

  • Page 101: Push To Stack

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PUSH — Push To Stack PUSH SP ← SP – 1 Operation: @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.

  • Page 102: Rcf - Reset Carry Flag

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Bytes Cycles...
  • Page 103 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Return PC ← @SP Operation: SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter.

  • Page 104: Rl - Rotate Left

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

  • Page 105: Rlc - Rotate Left Through Carry

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Rotate Left Through Carry dst (0) ← C Operation: C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C);...

  • Page 106: Rr - Rotate Right

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

  • Page 107: Rrc - Rotate Right Through Carry

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Rotate Right Through Carry dst (7) ← C Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag;...

  • Page 108: Sbc - Subtract With Carry

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

  • Page 109: Scf - Set Carry Flag

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Set Carry Flag C ← 1 Operation: The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format:...

  • Page 110: Sra - Shift Right Arithmetic

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 111: Stop - Stop Operation

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained.

  • Page 112: Sub - Subtract

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Subtract dst,src dst ← dst – src Operation: The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand.

  • Page 113: Tcm - Test Complement Under Mask

    SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Test Complement Under Mask dst,src (NOT dst) AND src Operation: This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

  • Page 114: Tm - Test Under Mask

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) SAM87RI INSTRUCTION SET — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.
  • Page 115 SAM87RI INSTRUCTION SET KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...
  • Page 116 Clock Circuit RESET and Power-Down I/O Ports Basic Timer and Timer 0 USB Block Universal Serial Bus Electrical Data Mechanical Data KS86P6008 OTP...

  • Page 117: Clock Circuit

    Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for KS86C6004/C6008/P6008, INT0–INT2). — In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags.

  • Page 118: System Clock Control Register (Clkcon)

    CLOCK CIRCUIT KS86C6004/C6008/P6008 MICROCONTROLLERS (Preliminary Spec) SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the following functions: — Oscillator IRQ wake-up function enable/disable (CLKCON.7) — Oscillator frequency divide-by value: non-divided, 2, 8 or 16 (CLKCON.4 and CLKCON.3) The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up"...
  • Page 119 KS86C6004/C6008/P6008 MICROCONTROLLERS (Preliminary Spec) CLOCK CIRCUIT STOP CLKCON.3, .4 Instruction Oscillator STOP MAIN CPU CLOCK Oscillator P3.3/CLO Wake-up 1/16 NOISE P3CON FILTER CLKCON.7 INT Pin Figure 7-3. System Clock Circuit Diagram...
  • Page 120 CLOCK CIRCUIT KS86C6004/C6008/P6008 MICROCONTROLLERS (Preliminary Spec) NOTES...

  • Page 121: Reset And Power-Down

    Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the KS86C6004/C6008/P6008 into a known operating status. The RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize.

  • Page 122: Power-Down Modes

    Using an External Interrupt to Release Stop Mode Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts INT0–INT2 in the KS86C6004/C6008/P6008 interrupt structure meet this criteria.

  • Page 123: Hardware Reset Values

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) RESET and POWER-DOWN HARDWARE RESET VALUES Tables 8-1 through 8-3 list the values for CPU and system registers, peripheral control registers and peripheral data registers following a reset operation in normal operating mode. The following notation is used in these tables to represent specific reset values: —...
  • Page 124 RESET and POWER-DOWN KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 8-1. Register Values After a Reset (continued) Bank 0 Register Name Mnemonic Address Bit Values After a Reset Port 3 control register P3CON Port 0 control register (high byte) P0CONH Port 0 control register (low byte)
  • Page 125 I/O PORTS OVERVIEW The KS86C6004/C6008/P6008 has five I/O ports (0–4) with a total of 32 pins. You can access these ports directly by writing or reading port data register addresses. For keyboard applications, ports 0, 1 and 2 are usually configured as keyboard matrix input/output. Port 3 can be configured as LED drive.

  • Page 126: Port Data Registers

    I/O PORTS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations and addressing characteristics. Data registers for ports 0–4 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary...
  • Page 127 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) I/O PORTS PORT 0 AND PORT 1 Ports 0 bit-programmable, general-purpose, I/O ports. You can select Schmitt trigger input mode, N-CH open drain output mode. You can access ports 0 and 1 directly by writing or reading the corresponding port data registers — P0 (E0H) and P1 (E1H).
  • Page 128 I/O PORTS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PORT 1 CONTROL REGISTERS P1CONH, E8H, R/W, P1CONL, E9H, R/W P1CONH P1.7 P1.6 P1.5 P1.4 P1CONL P1.3 P1.2 P1.1 P1.0 7,5,3,1 6,4,2,0 Port Mode Selection Schmitt trigger input mode Schmitt trigger input mode with pull-up...
  • Page 129 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) I/O PORTS PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger input mode or push-pull output mode). Or, you can use port 2 pins as external interrupt (INT0) inputs. In addition, you can configure a pull-up resistor to individual pins using control register settings.
  • Page 130 I/O PORTS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PORT 2 INTERRUPT ENABLE REGISTER (P2INT) ECH, R/W P2.0/ INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 Port 2 interrupt control settings: P2.6/INT0 0 = Disable interrupt at P2.n pin P2.7/INT0 1 = Enable interrupt at P2.n pin Figure 9-5.
  • Page 131 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) I/O PORTS PORT 3 Port 3 is a 4-bit, bit-configurable, general I/O port. It is designed for high-current functions such as LED drive. A reset configures P3.0–P3.3 to Schmitt trigger input mode. Using the P3CON register (E5H), you can alternatively configure the port 3 pins as n-channel, open-drain outputs.
  • Page 132 I/O PORTS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) PORT 4 Port 4 is a 4-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger, N-CH open drain output mode, push-pull output mode). Or, you can use port 4 pins as external interrupt (INT1) inputs.
  • Page 133 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) I/O PORTS PORT 4 INTERRUPT ENABLE AND PENDING REGISTER (P4INTPND) EFH, R/W P4.0/INT1 P4.1/INT1 P4.2/INT1 P4.3/INT1 P4.0/INT1 P4.1/INT1 P4.2/INT1 P4.3/INT1 P4INTPND.7 - 4 : Port 4 interrupt control settings: 0 = Disable interrupt at P4.n pin 1 = Enable interrupt at P4.n pin...
  • Page 134 I/O PORTS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) NOTES 9-10...

  • Page 135: Module Overview

    BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 MODULE OVERVIEW The KS86C6004/C6008/P6008 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. Basic Timer (BT) You can use the basic timer (BT) in two different ways: —...

  • Page 136: Basic Timer Control Register (Btcon)

    BASIC TIMER and TIMER 0 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function.

  • Page 137: Basic Timer Function Description

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B' (The '1010B' value disables the watchdog function). A reset clears BTCON to '00H', automatically enabling the watchdog timer function.
  • Page 138 BASIC TIMER and TIMER 0 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Oscillation stabilization time Normal operating mode 0.8 V DD Reset Release Voltage RESET trst ≈RC Internal Reset Release 0.8 V DD Oscillator (Xout) Oscillator stabilization time BTCNT clock 10000B BTCNT value...
  • Page 139 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) BASIC TIMER and TIMER 0 Normal Normal STOP mode Oscillation stabilization time operating operating mode mode STOP STOP mode instruction release signal execution External interrupt RESET STOP release signal Oscillator (Xout) BTCNT clock 10000B BTCNT 00000B...

  • Page 140: Timer 0 Control Register (T0Con)

    BASIC TIMER and TIMER 0 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) TIMER 0 CONTROL REGISTER (T0CON) T0CON is located at address D2H, and is read/write addressable. A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency of f /4096, and disables the timer 0 overflow interrupt and match interrupt.

  • Page 141: Timer 0 Function Description

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) BASIC TIMER and TIMER 0 TIMER 0 FUNCTION DESCRIPTION Interval Match Mode In interval match mode, a match signal is generated when the counter value is identical to the value written to the T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt and then clears the counter.
  • Page 142 BASIC TIMER and TIMER 0 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Bit 1 Write '1010xxxxB' to disable. RESET or STOP Data Bus Bits 7, 6, 5, 4 1/4096 8-Bit Basic Counter 1/1024 RESET (BTCNT Read-Only) 1/128 When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts.
  • Page 143 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) BASIC TIMER and TIMER 0 NOTES 10-9...

  • Page 144: Universal Serial Bus

    PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth through a host scheduled token based protocol. The USB module in KS86C6004/C6008/P6008 is designed to serve at a low speed transfer rate (1.5 Mbs) USB device as described in the Universal Serial Bus Specification Revision 1.0. KS86C6004/C6008/P6008 can be briefly describe as a microcontroller with SAM 87RI core with an on-chip USB peripheral as can be seen in figure 11-1.
  • Page 145 Data Transfer Types USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint supports a specific type of data transfer. The KS86C6004/C6008/P6008 supports two data transfer endpoints: control and interrupt. Control transfer configures and assigns an address to the device when detected. Control transfer also supports status transaction, returning status information from device to host.
  • Page 146 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) UNIVERSAL SERIAL BUS USB FUNCTION ADDRESS REGISTER (FADDR) This register holds the USB address assigned by the host computer. FADDR is located at address F0H and is read/write addressable. Bit7 Not used Bit6–0 FADDR: MCU updates this register once it decodes a SET_ADDRESS command. MCU must write this register before it clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0CSR register.
  • Page 147 UNIVERSAL SERIAL BUS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) CONTROL ENDPOINT STATUS REGISTER (EP0CSR) EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is located at F1H and is read/write addressable. Bit7 CLEAR_SETUP_END: MCU writes “1” to this bit to clear SETUP_END bit (bit4). This bit is automatically cleared after writing "1"...
  • Page 148 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) UNIVERSAL SERIAL BUS Control Endpoint Status Register (EP0CSR) F1H, R/W CLEAR_ OUT_PKT_RDY SETUP_END IN_PKT_RDY CLEAR_ OUT_PKT_RDY SENT_STALL SEND_STALL DATA_END SETUP_END Figure 11-3. Control Endpoint Status Register (EP0CSR) 11-5...
  • Page 149 UNIVERSAL SERIAL BUS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) INTERRUPT ENDPOINT STATUS REGISTER (EP1CSR) EP1CSR is the control register for Endpoint 1, Interrupt Endpoint. This register is located at address F2H and is read/write addressable. Bit7 CLEAR_DATA_TOGGLE: MCU writes “1” to this bit to clear the data toggle sequence bit. When the MCU writes a 1 to this register, the data toggle bit is initialized to DATA0.
  • Page 150 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) UNIVERSAL SERIAL BUS CONTROL ENDPOINT FIFO REGISTER (EP0FIFO) This register is bi-directional, 8-byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at address F4H and is read/write addressable. Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control transfer, that is, after MCU unload the setup data packet, and clears OUT_PKT_RDY, the direction of FIFO is changed automatically by the direction bit of data packet.
  • Page 151 UNIVERSAL SERIAL BUS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) USB INTERRUPT ENABLE REGISTER (USBINT) USBINT is located at address F7H and is read/write addressable. This register serves as an interrupt mask register. If the corresponding bit = 1 then the respective interrupt is enabled.
  • Page 152 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) UNIVERSAL SERIAL BUS USB POWER MANAGEMENT REGISTER (PWRMGR) PWRMGR register interacts with the Host’s power management system to execute system power events such as SUSPEND or RESUME. This register is located at address F8H and is read/write addressable.
  • Page 153 UNIVERSAL SERIAL BUS KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) USB RESET REGISTER (USBRST) USBRST register receives a reset signal from the Host when there has been no activities on UBS for a certain period of time. This register is located at address FFH and is read/write addressable.

  • Page 154: Electrical Data

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following KS86C6004/C6008/P6008 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — Input/Output capacitance — A.C. electrical characteristics — Input timing for external interrupt (Ports 0, 2, and 4) —...
  • Page 155 ELECTRICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 12-1. Absolute Maximum Ratings ° = 25 Parameter Symbol Conditions Rating Unit Supply Voltage – – 0.3 to + 6.5 Input Voltage All input ports – 0.3 to V + 0.3 Output Voltage All output ports –...
  • Page 156 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA Table 12-2. D.C. Electrical Characteristics ° ° = – 40 C to + 85 C, V = 4.5 V to 5.5 V) Parameter Symbol Conditions Unit Operating Voltage = 6 MHz (instruction clock = 1 MHz)
  • Page 157 ELECTRICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 12-3. Input/Output Capacitance ° ° = – 40 C to + 85 C, V = 0 V) Parameter Symbol Conditions Unit Input f = 1 MHz; Unmeasured pins – – Capacitance are connected to V...
  • Page 158 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA Table 12-5. Oscillator Characteristics ° ° = – 40 C + 85 C, V = 4.5 V to 5.5 V) Oscillator Clock Circuit Test Condition Unit Main crystal Main Oscillation frequency – – ceramic (f...
  • Page 159 ELECTRICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 12-7. Data Retention Supply Voltage in Stop Mode ° ° = – 40 C to + 85 Parameter Symbol Conditions Unit Data Retention Stop mode – DDDR Supply Voltage Data Retention Stop mode; V = 2.0 V...
  • Page 160 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA INTERNAL RESET IDLE MODE OPERATION (BASIC TIMER ACTIVE) STOP MODE DATA RETENTION MODE NORMAL DDDR OPERATING EXECUTION OF MODE STOP INSTRUCTION RESET 0.8 V 0.2 V WAIT Figure 12-4. Stop Mode Release Timing When Initiated by a Reset...
  • Page 161 ELECTRICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) Table 12-8. Low Speed Source Electrical Characteristics (1, 2, 3) Parameter Symbol Unit Conditions Driver Characteristics: (4, 5) Transition Time: , Figure 7-16 Rise Time CL = 50 pF – CL = 350 pF –...
  • Page 162 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA 12-9...

  • Page 163: Timing Waveforms

    ELECTRICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) TIMING WAVEFORMS PERIOD Crossover Points Differential Data Lines Consecutive Transitions N x T PERIOD xJR1 Paired Transitions N x T PERIOD xJR2 Figure 12-6. Differential Data Jitter PERIOD Crossover Points Extended Crossover Points Differential...
  • Page 164 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) ELECTRICAL DATA NOTES 12-11...

  • Page 165: Mechanical Data

    KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) MECHANICAL DATA MECHANICAL DATA OVERVIEW The KS86C6004/C6008/P6008 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin QFP package (44-QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2. 0-15 42-SDIP- 39.50 MAX 39.10 0.50...
  • Page 166 MECHANICAL DATA KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) 13.20 0-8° +0.10 0.15 - 0.05 10.00 44-QFP-1010B 0.10 MAX 0.05 MIN 2.05 0.10 +0.10 0.35 - 0.05 2.30 MAX (1.00) 0.80 NOTE : Dimensions are in millimeters. Figure 13-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
  • Page 167 OVERVIEW The KS86P6008 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS86C6004/C6008 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The KS86P6008 is fully compatible with the KS86C6004/C6008, both in function and in pin configuration.
  • Page 168 KS86P6008 OTP KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) P1.0 3.3 V P1.1 P1.2 P1.3 P3.3/CLO P1.4 P3.2 KS86P6008 P1.5 P3.1 (Top View) P1.6 P3.0 P1.7 P2.0/INT0 P4.3/INT1 P2.1/INT0 P4.2/INT1 P2.2/INT0 RESET/ RESET P2.3/INT0 Figure 14-2. KS86P6008 Pin Assignments (44-QFP Package) 14-2...

  • Page 169: Operating Mode Characteristics

    Entering) When writing 12.5 V is applied and when reading. 11(5)/12(6) – Logic Power Supply Pin. NOTE: ( ) means 44 QFP package. Table 14-2. Comparison of KS86P6008 and KS86C6004/C6008 Features Characteristic KS86P6008 KS86C6004/C6008 Program Memory 8-Kbyte EPROM 8-Kbyte mask ROM Operating Voltage (V 4.5 V to 5.5 V...
  • Page 170 KS86P6008 OTP KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) START Address= First Location =5V, V =12.5V x = 0 Program One 1ms Pulse Increment X x = 10 FAIL FAIL Verify Byte Verify 1 Byte Last Address Increment Address = 5 V FAIL...
  • Page 171 KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) KS86P6008 OTP Table 14-4. D.C. Electrical Characteristics ° ° = – 40 C to + 85 C, V = 4.5 V to 5.5 V) Parameter Symbol Conditions Unit Supply Current Normal mode; – (note) 6 MHz CPU clock Idle mode;...
  • Page 172 KS86P6008 OTP KS86C6004/C6008/P6008 MICROCONTROLLER (Preliminary Spec) NOTES 14-6...

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