Ipr Interrupt Priority Register - Samsung S3P80C5 User Manual

CONTROL REGISTERS
IPR
— Interrupt Priority Register
Bit Identifier
RESET Value RESET
Read/Write
Bit Addressing
.7, .4, and .1
.6
.5, .3
.2
.0
NOTE: The S3P80C5/C80C5/C80C8 interrupt structure uses only five levels:
IRQ0, IRQ1, IRQ4, IRQ6–IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and
group C settings (IPR.2,.3 and IPR.5) are not evaluated.
4-12
.7 .6
0 0
R/W R/W
Register addressing mode only
Priority Control Bits for Interrupt Groups A, B, and C
0 0 0 Group priority undefined
0 0 1 B > C > A
0 1 0 A > B > C
0 1 1 B > A > C
1 0 0 C > A > B
1 0 1 C > B > A
1 1 0 A > C > B
1 1 1 Group priority undefined
Interrupt Subgroup C Priority Control Bit
0 IRQ6 > IRQ7
1 IRQ7 > IRQ6
Not used for S3P80C5/C80C5/C80C8.
Input Group B Priority Control Bit
0 IRQ4
1 IRQ4
Interrupt Group A Priority Control Bit
0 IRQ0 > IRQ1
1 IRQ1 > IRQ0
.5 .4
0 0
R/W R/W R/W
S3P80C5/C80C5/C80C8
FFH
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W