Samsung S3P80C5 User Manual page 200

S3P80C5/C80C5/C80C8
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and
has the following functions:
— Oscillator frequency divide-by value
CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode
release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In
S3P80C5/C80C5/C80C8, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in
S3P80C5/C80C5/C80C8.
After a reset, the main oscillator is activated, and the f
clock. If necessary, you can then increase the CPU clock speed to f
System Clock Control Register (CLKCON)
MSB .7 .6 .5
Not used
Not used
Figure 7-4. System Clock Control Register (CLKCON)
/16 (the slowest clock speed) is selected as the CPU
OSC
OSC
D4H, Set 1, R/W
.4 .3 .2
Not used
Divide-by selection bits for
CPU clock frequency:
00 = f /16
OSC
01 = f /8
OSC
10 = f /2
OSC
11 = f (non-divided)
OSC
, f /2, or f /8.
OSC OSC
.1 .0 LSB
CLOCK CIRCUITS
7-3