Samsung S3P80C5 User Manual page 210

8-bit cmos microcontrollers
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S3P80C5/C80C5/C80C8
IDLE MODE
Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while
some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from
all but the following peripherals, which remain active:
— Interrupt logic
— Timer 0
— Timer 1
— Counter A
I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.
Idle Mode Release
You can release Idle mode in one of two ways:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slowest clock because of the hardware
reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the
only way you can release Idle mode.
2. Activate any enabled interrupt ; internal or external. When you use an interrupt to release Idle mode, the 2-bit
CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The
interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately
following the one which initiated Idle mode is executed.
Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode
without reset. To release Idle mode, you can use either an external interrupt or an internally-generated
interrupt.
NOTE
RESET
RESET
and POWER-DOWN
8-9

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