Samsung S3P80C5 User Manual page 77

CONTROL REGISTERS
P0CONH
— Port 0 Control Register (High Byte)
Bit Identifier
RESET Value RESET
Read/Write
Addressing Mode
.7–.6
.5–.4
.3–.2
.1–.0
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector
address (E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
4-14
.7 .6
0 0
R/W R/W
Register addressing mode only
P0.7/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
P0.6/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
P0.5/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
P0.4/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5 .4
0 0
R/W R/W R/W
S3P80C5/C80C5/C80C8
E8H
.3 .2 .1
0 0 0
R/W R/W
Set 1
.0
0
R/W