Csi Design Guidelines; Figure 10-2. Available Camera Control Pins; Table 10-3. Csi Configurations; Table 10-4. Mipi Csi Interface Signal Routing Requirements - Nvidia Jetson Orin NX Design Manual

Figure 10-2. Available Camera Control Pins
SoC
GP54_I2C3_CLK
GP55_I2C3_DAT
GP52_CLK1
GP121_UART4_CTS_N
GP53_CLK2
GP161_SPI5_CLK
Table 10-3. CSI Configurations
CSI0
Cameras CLK/Data[1:0]
2-Lanes Each
1 of 5 cameras √
2 of 5 cameras
3 of 5 cameras
4 of 5 cameras
5 of 5 cameras
4-Lanes Each
1 of 2 cameras √
2 of 2 cameras
10.1

CSI Design Guidelines

The following tables describe the design guidelines for the CSI design.
Table 10-4. MIPI CSI Interface Signal Routing Requirements
Parameter
Max Data Rate (per data lane) for High-Speed
mode
Max Frequency (for Low Power mode)
Number of loads
Reference plane
Trace impedance: Diff pair / SE
Via proximity (signal to reference)
Intra-pair trace spacing
Trace spacing: Microstrip / Stripline
Max PCB breakout delay
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Jetson
1.5kΩ
VDD_3V3_SYS
1.5kΩ
CAM_I2C_SCL
CAM_I2C_SDA
CAM0_MCLK
CAM0_PWDN
CAM1_MCLK
CAM1_PWDN
GP65
GP66
CSI1
CLK Data[1:0]
√
Requirement
2.5
10
1
GND
90-100 / 45-50
< 0.65 (3.8)
0.15mm
2x / 2x
48
Camera
213
I2C
215
Camera 0
116
Clock/Control
114
Camera 1
122
Clock/Control
120
GPIO01
Camera 2 Clock
118
GPIO11
Camera 3 Clock
216
CSI1 CSI2
CLK/Data[1:0]
√
√
√
√
Units Notes
Gbps
MHz
load
Ω ±10%
mm (ps)
mm Can be adjusted to meet Differential
Impedance.
dielectric
ps
MIPI CSI Video Input
CSI3 CSI3
CLK Data[1:0]
√ √
√
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