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2.6 MSMC Interrupt Control
Chapter 2—MSMC Architecture
2.6 MSMC Interrupt Control
2-18
KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide
The MSMC features a set of interrupt status and enable registers that can control the
generation of interrupts at the MSMC module boundary.
The MSMC interrupt operation is controlled by the registers listed in
described in
''MSMC Interrupt Control Registers''
Table 2-8
MSMC Interrupt Control Register List
Acronym
Register Description
SMESTAT
Interrupt Enabled Status register. ANDed value of SMIRSTAT and SMIESTAT registers
SMIRSTAT
Interrupt Raw Status register
SMIRC
Interrupt Raw Status Clear register. Writes of 0 have no effect.
SMIESTAT
Interrupt Enable Status register
SMIEC
Interrupt Enable Clear register
The SMIRSTAT register stores the raw interrupt status for each interrupt line, a bitfield
is set if the associated interrupt has occurred. An interrupt pulse can be generated and
its raw status recorded in SMIRSTAT either when the event occurs in hardware
(hardware interrupt) or when software writes to the associated bitfield in the
SMIRSTAT register (software interrupt for simulating the event). Regardless of how
the interrupt is generated, it is cleared by writing to the associated bit in the SMIRC
register.
The memory-protection-fault-interrupt event for each PrivID is
Note—
recorded in the SMIRSTAT and the associated address and master information
is logged into the SMPFAR and SMPFXR registers (see
Fault Reporting Registers''
SMPFAR and SMPFXR before clearing the corresponding bits for the PrivID
in the SMIRSTAT so that the event status and associated master information
are kept synchronized. This order is not enforced in hardware.
The SMIESTAT register stores the interrupt enable state for each of the interrupt lines;
a bitfield is set if the associated interrupt is enabled. The enable state can be set by
writing to the SMIESTAT register and cleared by writing to the SMIEC register.
For interrupt signalling and status capture the following rules apply:
•
For a given interrupt line, once an interrupt is signalled, its status is set and needs
to be cleared by the servicing host before another occurrence can be signalled.
The status for an interrupt line is set even if it is not enabled in the SMIESTAT.
Therefore, it is recommended that the software clears an interrupt status while
enabling it. This can be done atomically with a double-word-store writing to the
SMIESTAT and the SMIRC registers together.
•
Because there are three sources that can modify a bit in the SMIRSTAT, the
following precedence rules apply:
A hardware interrupt takes precedence over a software interrupt if they arrive
–
in the same cycle. This is not an intended usage mode as one would either
enable a hardware interrupt to signal a real hardware event or use a software
write to simulate the same event.
–
A write to set a event in the SMIRSTAT register takes precedence over
clearing an event in SMIRC register. This situation generates the interrupt
pulse corresponding to the event that is set.
on page 3-21.
on page 3-14). The software must clear the
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Table 2-8
and
''Memory Protection
SPRUGW7—November 2010
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